Abstract: The present invention discloses a layout method of a comparator array of a flash type analog to digital converting circuit. The flash type analog to digital converting circuit includes a reference voltage for generating 2n ?Ivoltages and being arranged to be folded; a comparator array including (2n?1) comparators for comparing voltage differences between the respective 2n ?Ivoltages and an analog input signal to generate a digital thermometer code having (2n?1) bits and an encoder for encoding the digital thermometer code having (2n?1) bits to generate an n-bit digital signal.

Abstract: The present invention relates to a method of source decoding variable-length codeword sequences, said decoding being based on an associated state diagram comprising a plurality of states (S) and on a code (C). It is characterized in that it comprises a step of reducing the states (S) in the state diagram in such a way that, at a bit time (Bj), only a number N of states in a group (G) of states is saved on the basis of a criterion derived from a partial metric computation and otherwise independently of an alphabet of said code (C), a group (G) being associated with a bit time (Bj). A group (G) corresponds to all the states (S) calculated at each bit time (Bj).

Abstract: An apparatus for producing a natural electromagnetic alternating field close to a user's body. The natural electromagnetic alternating field is similar to an area of pleasant weather (Sferics), to compensate for electrical stress acting on a user. The field can also be used for positive stimulation of the well-being of the user. The apparatus has a means for producing the alternating field and a means for transmitting the alternating field.

Abstract: An input changing switch is provided at a preceding stage of a comparator that measures a DC offset of a D/A converter, and also a selective polarity inverting circuit is provided at a subsequent stage. A first compensation value is generated by a compensation value generating means and then stored in a register. Then, a second compensation value is generated by switching the input changing switch and the polarity inverting circuit and then stored in a register. Then, a third compensation value is calculated by averaging the first compensation value and the second compensation value by a compensation value calculating circuit. Then, the DC offset of the D/A converter is compensated by using this compensation value. Therefore, it enables to implement a precise DC offset compensation of the D/A converter by canceling the DC offset contained in the comparator itself employed in the DC offset compensation of the D/A converter.

Abstract: A signal generator (1) for generating a square waveform analog voltage output signal comprises an on-chip DAC (12) which outputs the analog voltage signal on an output terminal (5). On-chip first and second programmable registers (9,10) store first and second digital words which correspond to the maximum and minimum voltage values of the analog output signal. An on-chip switch circuit (15) selectively and alternately switches the first and second registers (9,10) to an on-chip DAC register (17) from which the respective first and second digital words are loaded into the DAC (12) in response to a load DAC signal generated by a control circuit (14). The load DAC signal is generated in response to an externally generated LDAC signal in the form of a clock signal which is applied to an LDAC terminal (22). A flip-flop (19) in response to the load DAC signal outputs a control signal on a control line (25) for alternately switching the first and second registers (9,10) to the DAC register (17).

Abstract: Embodiments of a compression/decompression (codec) system may include a plurality of data compression engines each implementing a different data compression algorithm. A codec system may be designed for the reduction of data bandwidth and storage requirements and for compressing/decompressing data. Uncompressed data may be compressed using a plurality of compression engines in parallel, with each engine compressing the data using a different lossless data compression algorithm. At least one of the data compression engines may implement a parallel lossless data compression algorithm designed to process stream data at more than a single byte or symbol at one time. The plurality of different versions of compressed data generated by the different compression algorithms may be examined to determine an optimal version of the compressed data according to one or more predetermined criteria. A codec system may be integrated in a processor, a system memory controller or elsewhere within a system.

Abstract: A subranging analog to digital converter (ADC). The ADC (200) includes a novel resistive ladder (56) for a differential quantizer (50) and a novel summing node circuit (150). The novel resistive ladder (56) includes an input terminal (52), a plurality of serially connected resistors R coupled to the input terminal (52), and a pair of complementary current sources (66 and 68) for maintaining a constant current flow through the ladder (56). The novel summing node circuit (150) includes an input terminal (152) for receiving an input signal, a pair of complementary DACs (156 and 158) for generating a reconstruction signal, and a summing amplifier (164) for subtracting the reconstruction signal from the input signal to produce a residue signal. The invention also includes a method for trimming the subranging ADC.

Abstract: A compression/decompression (codec) engine is provided for use in conjunction with a fabric agent chip in a multiprocessor computer system. The fabric agent chip serves as an interface between a first memory controller on a first cell board in the computer system and other memory controllers on other cell boards in the computer system. Cell boards in the computer system are interconnected by a system fabric. Memory data read by the first memory controller is compressed by the codec engine prior to being transmitted over the system fabric by the fabric agent chip. Conversely, memory data received over the system fabric by the fabric agent chip is decompressed by the codec engine prior to being provided to the first memory controller. Other fabric agent chips in the computer system may similarly be provided with corresponding codec engines.

Abstract: An memory module including parallel data compression and decompression engines for improved performance. The memory module includes MemoryF/X Technology. To improve latency and reduce performance degradations normally associated with compression and decompression techniques, the MemoryF/X Technology encompasses multiple novel techniques such as: 1) parallel lossless compression/decompression; 2) selectable compression modes such as lossless, lossy or no compression; 3) priority compression mode; 4) data cache techniques; 5) variable compression block sizes; 6) compression reordering; and 7) unique address translation, attribute, and address caches. The parallel compression and decompression algorithm allows high-speed parallel compression and high-speed parallel decompression operation. The memory module-integrated data compression and decompression capabilities remove system bottlenecks and increase performance.

Abstract: The invention creates a method and a device for digitally transmitting analog signals, in which oversampling is performed in analog/digital and digital/analog converters. In this arrangement, a digital/analog conversion is performed which, in particular, is suitable for VDSL systems. A transmitted digital transmission signal (110) is supplied to a mixing unit (201) and in the mixing unit (201), a receive noise signal (211) applied to a receive noise source terminal (209) is superimposed on the digital transmission signal (110). An interpolation filter unit (203), in combination with a subsequent noise shaping device (205), provides an increase in the frequency bandwidth, resulting in suitable oversampling.

Abstract: An A-to-D converter system having programmed reference signal levels using only supply signal provided by a power supply is disclosed. The converter system includes a comparator configured to provide comparison of an analog input signal with an adjustable reference level. The converter system also includes a logic circuit and an adjustable capacitor.

Abstract: An adaptive analog-to-digital converter (ADC) system (100) includes an automatic gain control (AGC) controller (101) for receiving both in-band and out-of-band signals from a radio frequency (RF) receiver and producing an AGC control signal therefrom. A digital signal processor (DSP) (103) is then used for interpreting the AGC control signal and providing an adjustment signal to an ADC (105). The ADC (105) uses the adjustment signal to dynamically control efficiency of the ADC system 100 by adjusting bit resolution, reference capacitance and bias based upon the RF signal received and desired protocol requirements presented to the AGC controller (101).

Abstract: Non-ordinal conversion is performed between signals with at most one bit asserted and respective codes, such as between priority signals from a content addressable memory (CAM) priority encoder to respective non-ordinal codes. Address encoding includes non-ordinal conversion followed by recoding to obtain ordinal address codes. Signal converting circuitry includes neighboring switching elements such as transistors that are differently offset from neighboring input lines, allowing tight pitch between input lines. To allow for offset, each transistor can have no more than one neighboring transistor. For example, neighboring input lines can have complementary sets of transistors.

Abstract: In a code modulating method and a code modulating apparatus, a run length has an encoding rate of ? which is equal to that of (1, 7) modulation, and indicates the number of “0” bits between adjacent ones of “1” bits in the channel bit train. A data bit train is converted into the channel bit train so that the run length has a minimum value 1 and a maximum value 10. Further, upon converting any data bit train, the channel bit train does not include a pattern “1010101010101” in which the run length 1 is continuously repeated six times or more. The channel bit train has a DSV (Digital Sum Value) control bit which selects the “0” bit or “1” bit in accordance with a DSV. The channel bit train obtained by using random data for the data bit train is NRZI converted into a signal. A frequency component of the signal is reduced from a maximum value of the frequency component by 20 dB or less as a power density at a frequency of {fraction (1/10,000)} or less of a channel clock frequency.

Abstract: A variable bandgap reference includes a fixed bandgap reference source and a supply voltage dependent voltage divider module. The fixed bandgap produces a fixed reference voltage. The supply voltage dependent voltage adjust module adjusts the fixed reference voltage to produce the reference voltage.

Abstract: The present invention is a circuit for controlling current. In one embodiment, the high reference voltage input of a digital to analog converter is coupled with a reference voltage source which provides a positive reference voltage. A resistive load is coupled to an output of the digital to analog converter and to a circuit output pin. A sensing device couples the circuit output pin with the low reference voltage input of the digital to analog converter and to a reference ground input of the voltage source. The positive reference voltage, low reference voltage, and reference ground voltage are changed in response to the sensing device detecting a change in the output voltage.

Abstract: A rotary encoder has housing case provided with common electrode and signal electrode disposed to an area narrower than the entire circumference, or an angular range of generally ½ of the circumference in concentrical with central hole of housing case, and sliding contact in a confronting manner to the electrodes, the sliding contact provided with four combinations of contacts points arranged at four equally divided angular positions, or every 90 degrees along the same circumference about the rotary axis, each of the combinations comprises contact point on inner side for connectively sliding on common electrode and two contact points on outer side for connectively sliding on signal electrode. The rotary encoder of this structure can reduce the cost by decreasing a width of material needed for fabrication of electrodes, and decrease distances for contact points to slide on electrodes, to thereby improve durability to sliding abrasion.

Abstract: A data converter is implemented as an integrated circuit device (100). The converter comprises signal processing circuitry (120-170) which produces an output signal (OUT) in dependence upon a received input signal (D1-Dm). Production of the output signal (OUT) is initiated at a time determined by a timing signal (CLK) and is completed at a time which is delayed by a delay time with respect to the timing signal (CLK). A delay-contributing portion (130, 150, 160) makes a contribution to the delay time that is affected by variations in a power supply voltage (VDD) applied thereto. An internal supply voltage regulator (110) derives a regulated internal power supply voltage (VDD(REG)) from an external power source voltage (VDD), and applies this voltage to the delay-contributing portion (130, 150, 160) to fix its contribution to the delay time at some value independent of variations in the external power source voltage.

Abstract: A digital-analog converter (DAC) cell circuit. The circuit includes a current source, a first resistor, a second resistor, a first MOSFET, a second MOSFET, a third MOSFET and a forth MOSFET. The first MOSFET has a source and a drain connected to the current source and the first resistor, respectively, and a gate receiving a first control signal. The second MOSFET has a source and a drain connected to the current source and the second resistor, respectively, and a gate receiving a second control signal. The third MOSFET has a source and a drain connected to the source and drain of the first MOSFET, respectively, and a gate receiving a third control signal. The fourth MOSFET has a source and a drain connected to the source and drain of the second MOSFET, respectively, and a gate receiving a fourth control signal. The third control signal is a signal delayed of the first signal and the forth control signal is a signal delayed of the second signal.

Abstract: Methods and structures are provided for the interleaved calibration and subsequent correction of errors in switched-capacitor converter stages of pipelined analog-to-digital converters. The interleaved calibration can be run continuously or at selected times without disturbing the ongoing processing of input data signals. With first and second sets of capacitors, converter stages interleavably process input data signals and input calibration signals. Once these stages have been calibrated with their second sets of capacitors, the first and second sets are exchanged and the converter stages subsequently process input data signals with their second sets of capacitors.