Abstract: Techniques are provided for performing substitutions of bit sequences that are known to cause errors. Input data is initially modulation encoded. The modulated data is then analyzed in a sliding window to determine if it contains any additional bit sequences that are known to cause errors. If an error prone bit sequence is identified in the data, a substitution engine replaces the error prone bit sequence with a predetermined pattern of bits that is less likely to cause errors. The bit stream output of the substitution engine is then recorded on a storage medium. The recorded bit stream is decoded when it read from the medium. The decoding process identifies the substituted bit pattern and replaces the substituted pattern with the original sequence of bits.

Abstract: Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.

Abstract: A parallel decompression system and method that decompresses input compressed data in one or more decompression cycles, with a plurality of tokens typically being decompressed in each cycle in parallel. A parallel decompression engine may include an input for receiving compressed data, a history window, and a plurality of decoders for examining and decoding a plurality of tokens from the compressed data in parallel in a series of decompression cycles. Several devices are described that may include the parallel decompression engine, including intelligent devices, network devices, adapters and other network connection devices, consumer devices, set-top boxes, digital-to-analog and analog-to-digital converters, digital data recording, reading and storage devices, optical data recording, reading and storage devices, solid state storage devices, processors, bus bridges, memory modules, and cache controllers.

Abstract: An encoding system for determining position and position changes of a moving member has a sequence of encoder marks forming incremental patterns and at least one index pattern. Two subsequent incremental patterns are indicative of an incremental position-change of the moving member and the index pattern is indicative of a reference position of the moving member. A sensor arrangement views a section of the encoder-mark sequence, the length of which is greater than one position-change increment. An analyzer is arranged to analyze an encoder-mark pattern in the viewed section with regard to the incremental patterns and the index pattern and to generate, in response to a pattern match found, at least one of an incremental-position-change signal and an index signal.

Abstract: Techniques are provided for applying modulation constraints to data streams divided into separate interleaved portions. The even and odd bits in a data stream are separated into two data paths. A first modulation encoder encodes the even bits according to a first constraint. A second modulation encoder encodes the odd bits according to a second constraint. The two encoded data streams are then interleaved to form one data stream. The modulation encoders can encode the two data paths using Fibonacci encoding.

Abstract: An apparatus includes a delta-sigma analog-to-digital converter for digitalizing an analog input signal. The ?-? ADC includes an analog band-pass loop filter configured to filter an analog signal derived from the analog input signal and a quantizer configured to produce a series of digital signals by sampling the filtered analog signal from the loop filter at a sampling frequency. The loop filter has a center band-pass frequency. The series of digital signals has a data-carrying frequency spectrum that is a mirror image of a data-carrying frequency spectrum of the analog input signal. The data-carrying frequency spectrum of the series is located between the center band-pass frequency and zero.

Abstract: A clock signal duty cycle stabilization system. The system includes a clock signal duty cycle stabilization circuit having an edge detection circuit and a latch circuit. The edge detection circuit is configured to receive an external clock signal and generate an output therefrom. The latch circuit is coupled to receive the output from the edge detection circuit. The latch circuit is configured to produce a rising edge of an internal clock signal and a falling edge of the internal clock signal in accordance with the output of the edge detection circuit.

Abstract: A method and system for a feed-forward encoder is described. The method includes evaluating one or more source characters to determine whether each source character will invert or maintain a current running disparity and determining a running disparity for each source character before encoding the source character based on the current running disparity and whether the source character will invert or maintain the current running disparity. The current running disparity along with the associated source character may then be passed to an encoder to encode the source character into a transmission character.

Abstract: An Ethernet controller includes a decoder, and T sets of transmit circuits. Each set of transmit circuits receives one of T decoded signals from the decoder, and includes a digital-to-analog converter (DAC) that provides a transmit output signal, and a replica circuit that provides a replica output signal. Each DAC includes N current sources arranged in parallel and differentially, and M delay elements. Each current source includes a control input. A sum of outputs of the N current sources forms each transmit output signal. An input of the first delay element and the control input of the first current source receive a decoded signal. An input of an mth delay element is in communication with an output of an m?1th delay element. The output of each delay element controls a corresponding control input of a current source. A sum of the transmit output signals forms an accumulated output signal.

Abstract: An error correction circuit for use with an analog-to-digital converter (ADC) comprising a first switch and a second switch and correction capacitor arranged in parallel and coupled to the first switch. The second switch is also coupled to ground and the correction capacitor is also coupled to a reference voltage wherein the first switch is arranged to be active during a hold mode of the ADC and the second switch is arranged to be active during a sample phase of the ADC.

Abstract: We disclose a CIC digital filter having an arbitrary-integer decimation rate. The filter has a shifter connected to its input. The shifter receives a shift control input, where the shift control input is pre-computed as equal to the integer portion of 2 raised to the base-2 logarithm of the gain of the CIC filter. There is a multiplier connected between the input and the shifter. In other embodiments, the multiplier could be connected between the input and the shifter. Sequentially-connected integrator functions are connected to the shifter (or multiplier); a decimation function receives input from the integrator functions; and sequentially-connected differentiator functions receive input from the decimation function. The decimation function has a selectable rate equal to any integer between 1 and a number equal to the predetermined maximum decimation value.

Abstract: Apparatus for rapidly acquiring a large number of samples of a signal under test, stores the samples in a waveform memory without converting the samples to binary form. The signal under test is applied to an arrangement of comparators and exclusive-OR gates to provide a signal indicative of amplitude. The waveform memory is arranged in rows and columns. In one embodiment, the amplitude-indicative signal serves as a row address signal for the waveform memory, and a scanning control signal serves as a column address signal for the waveform memory. In another embodiment, an X-Y display is produced in which the column address signal is responsive to the amplitude of a second signal under test.

Abstract: A multi-mode analog to, digital converter (ADC). The novel ADC includes an input terminal for receiving an analog input signal; a plurality of processing stages, each processing stage adapted to generate an output signal from an input to that processing stage; and a mechanism for determining a mode of operation and in accordance therewith connect the processing stages and the input terminal in a predetermined configuration. In an illustrative embodiment, the ADC can be configured as a subranging ADC, and the mechanism for determining, the mode of operation includes a signal processor for automatically selecting the mode of operation based on the frequency components of the input signal.

Abstract: An aspect of the present invention provides multiple switches in a transceiver, which enable pins provided for transmission and reception to be connected to either a transmit port or a receive port, as desired during operation. As a result, the transceiver can be auto-configured to connect the specific pin, on which signals are being received, to the receive port. Similarly, the transceiver can be auto-configured to connect the specific pin, on which the signals need to be transmitted, to the transmit port. Various design considerations in providing such switches are also described.

Abstract: A DAC architecture is described. The architecture is specifically adapted to provided an analog voltage output based on a digital input word. The architecture includes a resistor ladder configuration sub-divisible into a first component, adapted to convert a lower part of the input word, and a second component adapted to convert an upper part of the input word. The DAC is calibrated such that the first component can be used to tune the output of the second component on selection of specific segment from the second component.

Abstract: An Ethernet controller includes a decoder, and T sets of transmit circuits. Each set of transmit circuits receives one of T decoded signals from the decoder, and includes a digital-to-analog converter (DAC) that provides a transmit output signal, and a replica circuit that provides a replica output signal. Each DAC includes N current sources arranged in parallel and differentially, and M delay elements. Each current source includes a control input. A sum of outputs of the N current sources forms each transmit output signal. An input of the first delay element and the control input of the first current source receive a decoded signal. An input of an mth delay element is in communication with an output of an m?1th delay element. The output of each delay element controls a corresponding control input of a current source. A sum of the transmit output signals forms an accumulated output signal.

Abstract: An A/D converter includes a low-bit resolution A/D which converts an input signal into a digital value of 4 bits or less, and a low-pass digital filter which suppresses a high-frequency-band component in an output from the low-bit resolution A/D, and extracts phase information contained in the input signal as amplitude information. A digital PLL circuit and information recording apparatus are also disclosed.

Abstract: An enhancement that reduces the digital interface rate of analog-to-digital (A/D) and digital-to-analog (D/A) converters through the use of compression and decompression is described. The present invention improves A/D converters by compressing the sampled version of the A/D converter's analog input signal in real time, thereby significantly decreasing the required bit rate of the A/D converter's digital interface. Similarly, the present invention improves D/A converters by decreasing the required bit rate of the D/A converter's digital interface. D/A converters enhanced by the present invention include a decompressor that decompresses the D/A converter's compressed digital input in real time, prior to conversion to an analog output signal. The present invention's simplicity and its ability to be implemented using multiple compression and decompression elements allow its use in A/D and D/A converters with arbitrarily high sampling rates.

Abstract: A first amplifier circuit amplifies an input signal by a factor of ?. A first AD converter circuit is configured at an LSB voltage of VA and converts an input analog signal into a digital value of arbitrary N1 bits. A first DA converter circuit converts the digital value output from the first AD converter circuit into an analog signal. A subtracter circuit subtracts an output of the first DA converter circuit from an output of the first subtracter circuit. A second amplifier circuit amplifies an output of the subtracter circuit by a factor of ?. A second AD converter is configured at an LSB voltage of VB and converts an input analog signal into a digital value of arbitrary N2 bits. In this circuit, the relation VA*?*?=VB*2N2 holds.

Abstract: In a test circuit, a determination circuit conducts a function test to determine whether timing of a slope section of waveform of an analog signal ANS of a measurement target device is within a range of specifications. An ADC performs AD-conversion only when a potential of analog signal ANS is within a range between reference potentials VOL, VOH. An analysis unit analyzes digital data from the ADC, and conducts a sloping waveform test to evaluate a sloping state of the waveform of analog signal ANS. Therefore, the slope section of the waveform of analog signal ANS of the device can be subjected to AD-conversion in a voltage range divided in arbitrary number of sections within a range of arbitrary voltage amplitude without requiring a large-capacity storage circuit. The function test by a determination circuit and the sloping waveform test by the analysis unit can be performed in parallel.