Abstract: A source signal is provided. The source signal is XORed with a scrambling random signal to generate a scrambled signal. The scrambled signal is transmitted through the digital logic circuit. The scrambled signal is XORed with the descrambling random signal logically identical to the scrambling random signal to produce a descrambled signal identical to the source signal. In one embodiment, the scrambling random signal is transmitted through the digital logic circuit and used as the descrambling random signal. In another embodiment, the scrambling random signal and descrambling random signal are generated independently using pseudo-random number generators. In yet another embodiment, the scrambling random signal is self-synchronizing and is contained within the pattern of the scrambled signal.

Abstract: A frequency-controlled load driver circuit includes a steady-state and a transient operational mode. A switching driver switches a load current to a solenoid at a set switching frequency during a steady-state operational mode. An analog-to-digital converter (ADC) oversamples a sense resistor voltage an integer number of times within each period of the switching frequency. A control circuit sets the switching frequency of the driver during the steady-state operational mode by providing predetermined switching times. The control circuit disables switching during the transient mode. Dither can be applied during the steady-state mode.

Abstract: Methods and apparatus for varying and measuring the position of a micromachined electrostatic actuator using a pulse width modulated (PWM) pulse train are disclosed. One or more voltage pulses are applied to the actuator. In each of the pulses, a voltage changes from a first state to a second state and remains in the second state for a time tpulse before returning to the first state. The position of the actuator may be varied by varying the time ?tpulse. A position of the actuator may be determined by measuring a capacitance of the actuator when the voltage changes state, whether the time t is varied or not. An apparatus for varying the position of a MEMS device may include a pulse width modulation generator coupled to the MEMS device an integrator coupled to the MEMS device and an analog-to-digital converter coupled to the integrator. The integrator may measure a charge transferred during a transition of a pulse from the pulse generator.

Abstract: A fourth order delta sigma analog-to-digital converter is presented, comprising a passive delta sigma modulator including a passive filter, a quantizer, and a digital-to-analog converter in a first feedback loop, and an active filter having a large gain factor in a second feedback loop around the passive delta-sigma modulator.

Abstract: A series capacitive component for use in signal processing applications such as analog-to-digital (A/D) converters, switched capacitor circuits and the like that require matched capacitors is presented. A series capacitive component consists of multiple capacitors connected in series. By utilizing series capacitive components in integrated circuits, significantly lower loads are provided for the same resulting capacitor mismatch range as previous solutions. Additionally, for the same load and noise, using series capacitive components provides a substantially reduced match over previous solutions. Thus a circuit designer has more flexibility when making tradeoffs between circuit area and capacitor mismatch and therefore manufacturing yields.

Abstract: The present invention relates to a sensor apparatus capable of outputting an accurate sensor signal irrespective of a variation of power supply voltage. In the sensor apparatus, when an A/D conversion circuit produces and outputs digital data, a switch circuit is placed into a first switching condition so that a constant voltage is applied from a constant-voltage circuit to an oscillation circuit, and a stabilized oscillation frequency is outputted from the oscillation circuit to the A/D conversion circuit. Thus, even if a power supply voltage varies, the A/D conversion circuit carries out sampling processing on analog data on the basis of the stabilized oscillation frequency from the oscillation circuit to produce and output the digital data.

Abstract: A comparator is arranged to compare a series of analog voltage signal samples on a first capacitor with a voltage on a second capacitor which is linearly increased or decreased to equal the sample value. The comparator's single output freezes the count of the counter at counts which are proportional to the voltage of the respective samples. In this manner, analog to digital conversion can be accomplished using a single line between the analog and digital sides of a circuit, thereby reducing parasitic capacitance.

Abstract: A method and apparatus reduces a DC level of an input word. The input word is divided into a plurality of components that include n symbols. The n symbols of the components are summed for each component. The component is encoded into a substitute component if a sum for the component exceeds a threshold. The components having a sum that does exceed the threshold are combined with at least one substitute component into an output word. An output word template is selected based on a number of substitute components and on a position that the substitute components originally occupied in the input word. The substitute components are inserted in the output word template. The components that have a sum that does not exceed the threshold are inserted in the output word template. Address and indicator symbols are inserted in the output word.

Abstract: Data destined for a client is compressed at a server in a manner that produces a compressed data string that can be searched in its compressed state. The server constructs a code table that assigns codes from a standard code set (e.g., ASCII code set) that are normally unused to selected character pairs in the data string (e.g., the most frequently occurring character pairs). During compression, the selected character pairs are replaced with the corresponding codes. Identifiers are inserted into the compressed data string to separate substrings. To search the compressed data string at the client, a search query is compressed and compared to the compressed substrings. The substring identifiers are used to quickly locate each successive compressed substring. When a match is found, the matching substring is decompressed by replacing the code in the compressed substring with the corresponding character pair in the code table.

Abstract: A method and apparatus for calibrating an electronic circuit which required scaled matching of some or all of its electronic components with nonvolatile programmably trimmable parameter sources (current, voltage, resistance, capacitance) is carried out in a top-down (highest order bit first, lowest order bit last) fashion without an analog division step. The method and apparatus are applicable, for example, to current-steering digital-to-analog converters (DACs), voltage-controlled oscillators (VCOs), voltage-steering DACs, and the like. In each of these applications the method and apparatus is used to match successive device outputs according to a desired scale factor, proceeding top-down from large output devices to smaller output devices, thereby successively shrinking the cross-device errors which accrue during the matching process.

Abstract: A multi-channel dual slope analog-digital converter with offset cancellation an hysteresis input is provided in the present invention, wherein a charge reset period and an auto zero period are eliminated, so as to shorten cycle time. An offset cancel capacitor is also eliminated, so that large chip area is avoided. With inserting a dummy cycle in between each measurement cycle, coupling error can be avoided between different conversion channels. Also, hysteresis property of a Schmitt comparator in the comparator unit manages to filter out minute residual voltage offset, so that the output of converter retains its residual voltage level. A multi-channel dual slope analog-digital converting method is also provided in the invention.

Abstract: Dithering techniques that efficiently combine a non-correlated noise signal with a desired signal are disclosed. Insertion loss in the noise path is relatively low due to combining means employed. In one embodiment, a self-contained dithering module includes a diplexer (or equivalent device) that provides an insertion loss associated with the noise signal of 3 dB or less. The signal+noise output can be used in noise-based application such as a data conversion process.

Abstract: Lossless data compression system comprising a content addressable memory dictionary, a coder, and a run length encoder connected to receive the output of the coder. The encoder is arranged to count the number of times a match consecutively occurs at a predetermined dictionary location, i.e. the number of times the same search tuple is loaded into the same address of the dictionary. Compression is improved.

Abstract: According to some embodiments, a successive approximation analog-to-digital converter is provided.

Abstract: The present invention discloses a flash type analog to digital converting method, comprising: (a) receiving an analog signal and generating 128-bit digital thermometer code based on the analog signal; (b) 3rd-compressing the 128-bit thermometer code to generate a 16-bit thermometer code and a 3-bit carry; and (c) encoding the 128-bit thermometer code to generate a 7-bit digital signal. Therefore, a layout area can be reduced because, after a 2n-bit thermometer code is compressed, the compressed digital signal is encoded to generate an n-bit digital signal.

Abstract: A data conversion apparatus of this invention has a storage unit configured to store a conversion table to convert m-bit data into n-bit data, and a conversion unit configured to convert the m-bit data into the n-bit data by using the conversion table stored in the storage unit. The conversion table contains a plurality of bit conversion codes to convert the m-bit data into the n-bit data. The bit conversion code is a code which converts the m-bit data into the n-bit data that allows the minimum number d of consecutive “0” bits between “1” bits.

Abstract: Digital signals of the most significant bit to the least significant bit are supplied to a digital calibration operation unit from a redundancy correction circuit, and an intermediate high order 2-bit digital signal is supplied to a correction value selection circuit. A DC control signal is supplied to the correction value selection circuit. A plurality of groups of correction values corresponding to the values of the intermediate high order 2-bit digital signal are stored in advance in a correction value ROM. The correction value selection circuit reads out a correction value from the correction value ROM based on the DC control signal and the intermediate high order 2-bit digital signal. The digital calibration operation unit adds the correction value AM to the digital signals of the most significant bit to the least significant bit, and outputs a resulting value as a digital output value.

Abstract: A method for generating a modulo Gray-code representation of a non-power-of-two set of binary values begins by determining a desired Gray-code sequence length. The method then continues by determining a bus width, M, in bits, based on the desired Gray-code sequence length, to represent the generated Gray-code. The method then continues by determining a set of skipped binary values based on the desired Gray-code sequence length and the bus width to obtain the non-power-of-two set of binary values. The method then continues by representing the non-power-of-two set of binary values as a set of equivalent Gray-code values.

Abstract: A method and apparatus control switching noise in a digital-to-analog interface in a mixed-signal circuit. The digital-to-analog interface includes a first plurality (K) of switching elements and a second plurality (M) of dummy switching elements, the second plurality (M) being smaller than the first plurality (K). The switching noise control includes (a) receiving a digital data signal, (b) determining a number (N) of the switching elements to be switched for the digital data signal, and (c) switching the second plurality (M) less the number (N) of the dummy switching elements simultaneously with switching the number (N) of the switching elements.

Abstract: The invention comprises an array of ADCs, associated either with spatially separated signal input devices such as for example antennae, or with a single signal input device and a plurality of filters having a variable phase delay, which provide a digital output which is processed to remove spurious signals introduced by the ADCs thereby providing a linearised output. An array of N antennae with respective band pass filters and ADCs (10) feeds received signals into a frequency channelisation device (12) which divides each of the N input streams into M lower bandwidth streams for distribution. In a first path, an FFT (14) is used to detect signal of interest, to determine where intermodulation products arm likely to exist and to provide course data for the spatial processing used in the signal separation sub-systems. The second path (16) includes the detection and separation of co-channels signals. Signal classification techniques are then used to identify spurious sir, which are then removed.