Abstract: Disclosed is a sputtering target that can suppress the occurrence of anomalous discharge in the formation of an oxide semiconductor film by sputtering method and can continuously and stably form a film. Also disclosed is an oxide for a sputtering target that has a rare earth oxide C-type crystal structure and has a surface free from white spots (a poor appearance such as concaves and convexes formed on the surface of the sputtering target). Further disclosed is an oxide sintered compact that has a bixbyite structure and contains indium oxide, gallium oxide, and zinc oxide. The composition amounts (atomic %) of indium (In), gallium (Ga), and zinc (Zn) fall within a composition range satisfying the following formula: In/(In+Ga+Zn)<0.75.

Abstract: An LED module includes a plurality of lighting sources each including a substrate, a first and second lead frames arranged on the substrate, an LED chip electrically connected to the first and the second lead frames, and an encapsulation covering the LED chip. The first lead frame of each of the lighting sources connects with the second lead frame of an adjacent lighting source electrically and mechanically.

Abstract: A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.

Abstract: A device and method for semiconductor fabrication includes forming a buffer layer on a semiconductor substrate and depositing an amorphous elemental layer on the buffer layer. Elements of the elemental layer are diffused through the buffer layer and into the semiconductor layer.

Abstract: A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer.

Abstract: A memristive device includes a first and a second electrode; a silicon memristive matrix interposed between the first electrode and the second electrode; and a mobile dopant species within the silicon memristive matrix which moves in response to a programming electrical field and remains substantially in place after the removal of the programming electrical field. A method for using a crossbar architecture containing a silicon memristive matrix includes: applying a programming electrical field by applying a voltage bias across a first conductor and a second conductor; a silicon memristive matrix containing mobile dopants being interposed between the first conductor and the second conductor, the programming voltage repositioning the mobile dopants within the silicon memristive matrix; and reading a state of the silicon memristive matrix by applying a reading energy across the silicon memristive matrix, the reading energy producing a measurable indication of the state of the silicon memristive matrix.

Abstract: A device includes a first source/drain region of a first conductivity type over a silicon substrate, wherein the first source/drain region is at a higher step of a two-step profile. The first source/drain region includes a germanium-containing region. A second source/drain region is of a second conductivity type opposite the first conductivity type, wherein the second source/drain region is at a lower step of the two-step profile. A gate dielectric includes a vertical portion in contact with a side edge the silicon substrate, and a horizontal portion in contact with a top surface of the silicon substrate at the lower step. The horizontal portion is connected to a lower end of the vertical portion. A gate electrode is directly over the horizontal portion, wherein a sidewall of the gate electrode is in contact with the vertical portion of the gate dielectric.

Abstract: The present disclosure provides a method of fabricating a semiconductor device that includes providing a semiconductor substrate, forming a metal gate on the substrate, the metal gate having a first gate resistance, removing a portion of the metal gate thereby forming a trench; and forming a conductive structure within the trench such that a second gate resistance of the conductive structure and remaining portion of the metal gate is lower than the first gate resistance.

Abstract: A triplet light emitting device which has high efficiency and improved stability and which can be fabricated by a simpler process is provided by simplifying the device structure and avoiding use of an unstable material. In a multilayer device structure using no hole blocking layer conventionally used in a triplet light emitting device, that is, a device structure in which on a substrate, there are formed an anode, a hole transporting layer constituted by a hole transporting material, an electron transporting and light emitting layer constituted by an electron transporting material and a dopant capable of triplet light emission, and a cathode, which are laminated in the stated order, the combination of the hole transporting material and the electron transporting material and the combination of the electron transporting material and the dopant material are optimized.

Abstract: Methods and structures for a double-sided semiconductor structure using through-silicon vias (TSVs) are disclosed. The double-sided structure has functional circuits on both the front and back sides, interconnected by one or more TSVs. In some embodiments, multiple double-sided structures are combined to create 3D semiconductor structures with increased circuit density.

Abstract: In one embodiment, a semiconductor device includes a well region of a second conductivity type, a control electrode, a first main electrode and a second main electrode. The well region has a source region and a drain region of a first conductivity type selectively formed in a surface of the well region. The control electrode is configured to control a current path between the source region connected to the first main electrode and the drain region connected to the second main electrode. With respect to a reference defined as a position of the well region at an identical depth to a portion of the source region or the drain region with maximum curvature, a peak of impurity concentration distribution of the second conductivity type is in a range of 0.15 micrometers on a side of the surface of the well region and on a side opposite to the surface.

Abstract: A process for fabricating a charge storage layer comprising metal particles of a memory cell, said layer consisting of an organic layer comprising, on the surface, said metal particles, said process comprising the following steps: (a) a step of grafting, onto a metallic, semiconductor or electrically insulating substrate, an organic layer comprising, on the surface, groups capable of complexing at least one metallic element in cationic form; (b) a step of bringing said layer into contact with a solution comprising said metallic element in cationic form, by means of which said metallic element is complexed by said abovementioned groups; and (c) a step of reducing said complexed metallic element to the metallic element in oxidation state 0, by means of which metal particles are obtained.

Abstract: A method of manufacturing a compound semiconductor device, includes: forming a compound semiconductor lamination structure over a substrate; forming a metal film over the compound semiconductor lamination structure; forming a source electrode and a drain electrode over the metal film; forming one of a metal oxide film and a metal nitride film by one of oxidizing and nitriding a part of the metal film; and forming a gate electrode over the metal oxide film or the metal nitride film.

Abstract: A semiconductor device having an electrical fuse which is cut in a reliable manner and a method for manufacturing it. The electrical fuse is a multilayer structure which includes a polysilicon film and a metal silicide film such as a tungsten silicide film. By applying an electric current with a density of 40 mA/?m3 or more to the electrical fuse with a prescribed length, the fuse is cut by electromigration and a pinch effect in a reliable manner.

Abstract: An image processing apparatus for performing an image processing on a body cavity image captured in a living body includes: a storage unit which stores information including image information of the body cavity image; a change amount calculator which reads out the image information of the body cavity image from the storage unit and calculates, in the read body cavity image, a pixel value change amount of a pixel of interest with a plurality of surrounding pixels located around the pixel of interest; and a candidate lesion region detector which detects a candidate lesion region in the body cavity image based on calculation result of the change amount calculator.

Abstract: A nanowire field effect transistor (FET) device includes a channel region including a silicon nanowire portion having a first distal end extending from the channel region and a second distal end extending from the channel region, the silicon portion is partially surrounded by a gate stack disposed circumferentially around the silicon portion, a source region including the first distal end of the silicon nanowire portion, a drain region including the second distal end of the silicon nanowire portion, a metallic layer disposed on the source region and the drain region, a first conductive member contacting the metallic layer of the source region, and a second conductive member contacting the metallic layer of the drain region.

Abstract: Shallow trenches are formed around a vertical stack of a buried insulator portion and a top semiconductor portion. A dielectric material layer is deposited directly on sidewalls of the top semiconductor portion. Shallow trench isolation structures are formed by filling the shallow trenches with a dielectric material such as silicon oxide. After planarization, the top semiconductor portion is laterally contacted and surrounded by the dielectric material layer. The dielectric material layer prevents exposure of the handle substrate underneath the buried insulator portion during wet etches, thereby ensuring electrical isolation between the handle substrate and gate electrodes subsequently formed on the top semiconductor portion.

Abstract: Fabricating a semiconductor device includes: forming a gate trench in an epitaxial layer overlaying a semiconductor substrate; depositing gate material in the gate trench; forming a body in the epitaxial layer; forming a source embedded in the body; forming a contact trench that extends through the source and at least part of the body; forming a body contact implant on a sidewall of the contact trench; forming a diode enhancement layer along bottom of the contact trench, the diode enhancement layer having opposite carrier type as the epitaxial layer; disposing an epitaxial enhancement portion below the diode enhancement layer, the epitaxial enhancement portion having the same carrier type as the epitaxial layer; and disposing a contact electrode in the contact trench; wherein: a distance between top surface of the substrate and bottom of the epitaxial enhancement layer is shorter than a distance between the top surface of the substrate and bottom of the body.

Abstract: A thermally conductive LED assembly is disclosed. The thermally conductive LED assembly includes an elongate conductor cable having a first conductor and a second conductor extending along a length of the elongate conductor cable and a thermally conducting and electrically insulating polymer layer disposed between first conductor and second conductor and a second electrically insulating polymer layer is disposed on the first conductor or second conductor. The electrically insulating polymer layer having a thermal impedance value in a range from 2.5 to 15 C.°-cm2/W and a plurality of light emitting diodes are disposed along the length of the elongate conductor cable. Each light emitting diode is in electrical communication with the first conductor and the second conductor.

Abstract: A semiconductor light-emitting device and a method for manufacturing the same can include a wavelength converting layer in order to emit various colored lights including white light. The device can include a board, a frame located on the board, at least one light-emitting chip mounted on the board, the wavelength converting layer located between an optical plate and an outside surface of the chips so that a density of a peripheral region is lower than that of a middle region, and a reflective material layer disposed at least between the frame and a side surface of the wavelength-converting layer. The device can have the reflective material layer form each reflector and can use a wavelength converting layer having different densities, and therefore can emit a wavelength-converted light having a high light-emitting efficiency and a uniform color tone from various small light-emitting surfaces.