Abstract: The present invention relates to a nitride semiconductor light emitting device including: a first nitride semiconductor layer having a super lattice structure of AlGaN/n-GaN or AlGaN/GaN/n-GaN; an active layer formed on the first nitride semiconductor layer to emit light; a second nitride semiconductor layer formed on the active layer; and a third nitride semiconductor layer formed on the second nitride semiconductor layer. According to the present invention, the crystallinity of the active layer is enhanced, and optical power and reliability are also enhanced.

Abstract: A backside illuminated sensor includes a semiconductor substrate having a front surface and a back surface and a plurality of pixels formed on the front surface of the semiconductor substrate. A dielectric layer is disposed above the front surface of the semiconductor substrate. The sensor further includes a plurality of array regions arranged according to the plurality of pixels. At least two of the array regions have a different radiation response characteristic from each other, such as the first array region having a greater junction depth than the second array region, or the first array region having a greater dopant concentration than the second array region.

Abstract: A process for burying a tungsten member into a blind hole formed in a wafer, in which blind hole a through via is to be made. Film-formation (for forming the tungsten member) is carried out to position, at the periphery of the wafer, the outer circumference of the tungsten member inside the outer circumference of a barrier metal beneath the tungsten film. This process makes it possible to bury the tungsten member, which may be relatively thin, into the blind hole, which may be relatively large, so as to decrease a warp of the wafer and further prevent an underlying layer beneath the tungsten member from being peeled at the periphery of the wafer.

Abstract: In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.

Abstract: Methods and devices for correcting wear pattern defects in joints. The methods and devices described herein allow for the restoration of correcting abnormal biomechanical loading conditions in a joint brought on by wear pattern defects, and also can, in embodiments, permit correction of proper kinematic movement.

Abstract: A more convenient and highly reliable semiconductor device which has a transistor including an oxide semiconductor with higher impact resistance used for a variety of applications is provided. A semiconductor device has a bottom-gate transistor including a gate electrode layer, a gate insulating layer, and an oxide semiconductor layer over a substrate, an insulating layer over the transistor, and a conductive layer over the insulating layer. The insulating layer covers the oxide semiconductor layer and is in contact with the gate insulating layer. In a channel width direction of the oxide semiconductor layer, end portions of the gate insulating layer and the insulating layer are aligned with each other over the gate electrode layer, and the conductive layer covers a channel formation region of the oxide semiconductor layer and the end portions of the gate insulating layer and the insulating layer and is in contact with the gate electrode layer.

Abstract: A support substrate comprises first and second counter-electrodes arranged in the same plane at the level of a surface of the support substrate. An electrically insulating area separates the first and second counter-electrodes. A semi-conducting area with first and second portions is separated from the support substrate by an electrically insulating material. The electrically insulating material is different from the material forming the support substrate. The first portion of the semi-conducting area is facing the first counter-electrode. The second portion of the semi-conducting area is facing the second counter-electrode.

Abstract: A method for reducing a disturbance in an input signal caused by an output signal in a multi-port connector, a multi-port connector circuit for reducing a disturbance in an input signal caused by an output signal, and a mobile device are described.

Abstract: A method of bonding metal and glass using an optical contact bonding includes depositing an optical contact bonding medium on a surface of a metal substrate; and bonding the metal substrate on which the optical contact bonding medium is formed to a glass substrate using optical contact bonding.

Abstract: An electrostatic discharge semiconductor device can include a first conductivity type substrate that includes inner first conductivity type wells therein and a plurality of gate electrodes that are on an active region of the substrate. A second conductivity type well can be located in the substrate beneath the plurality of gate electrodes including at least one slit therein providing electrical contact between the inner first conductivity type wells and a first conductivity type outer well outside the active region.

Abstract: An organic light emitting display apparatus has a hybrid structure in which resonance red, green and blue pixels and a non-resonance white pixel are combined. An optical path control layer and a white color filter which selectively absorbs light having a specific wavelength are included in the white pixel. Thus, the organic light emitting display apparatus has a large viewing angle, low power consumption, and long lifetime.

Abstract: A flip chip package structure includes a chip placed under a lead frame, a bump on the upper surface of the chip that is electrically connected to the lead of the lead frame, and a backside metal on the lower surface of the chip that is exposed outside an encapsulant encapsulating the chip and a portion of the lead frame.

Abstract: A fabricating method of CMOS transistor includes following steps. A first gate and a second gate are formed on a substrate. A gate insulator is formed on the substrate to cover the first and second gates. A first source, a first drain, a second source, and a second drain are formed on the gate insulator. The first source and the first drain are above the first gate. The second source and the second drain are above the second gate. A first channel layer and a mask layer are formed on the gate insulator. The mask layer is on the first channel layer. The first channel layer is above the first gate and contacts with the first source and the first drain. A second channel layer is formed on the gate insulator. The second channel layer is above the second gate and contacts with the second source and the second drain.

Abstract: Contact elements of sophisticated semiconductor devices may be formed for gate electrode structures and for drain and source regions in separate process sequences in order to apply electroless plating techniques without causing undue overfill of one type of contact opening. Consequently, superior process uniformity in combination with a reduced overall contact resistance may be accomplished. In some illustrative embodiments, cobalt may be used as a contact metal without any additional conductive barrier materials.

Abstract: The invention provides a SONOS structure, a manufacturing method thereof and a semiconductor device with the SONOS structure. The SONOS structure comprises: a first tunneling oxide layer formed on a substrate, a charge storage silicon nitride layer, a second silicon oxide layer, a thin graded silicon nitride layer having graded Si/N content formed on the second silicon oxide layer, a third silicon oxide layer formed on the thin graded silicon nitride layer, and a polysilicon control gate. The Si/N content ratio of the silicon nitride of the thin graded silicon nitride layer increases gradually, wherein the silicon nitride of the graded silicon nitride layer closer to the second silicon oxide layer contains higher nitride content, and the silicon nitride of the graded silicon nitride layer closer to the third silicon oxide layer contains higher silicon content.

Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate and forming a trench in the resistor and into the substrate. The method also includes forming a liner on sidewalls of the trench and forming a core comprising a high thermal conductivity material in the trench and on the liner.

Abstract: A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure.

Abstract: Methods and structure for adapting MEMS structures to form electrical interconnections for integrated circuits. A first portion and a second portion of the metal conductor, which can be electrically isolated within a CMOS IC device, can be etched to form an unetched portion of the metal conductor. The MEMS device can be patterned, from a MEMS layer formed overlying the metal conductor, via a plasma etching process, during which the unetched portion of the metal conductor is protected from the plasma. The metal conductor can be electrically coupled to the CMOS IC device via a conductive jumper or the like. Furthermore, the integrated CMOS-MEMS device can include a MEMS device coupled to a CMOS IC device via an electrically isolated metal conductor within the CMOS IC device. Also, the metal conductor can be electrically coupled to the substrate of the CMOS IC device via a conductive jumper.

Abstract: A nitride-based semiconductor light-emitting element LE1 or LD1 has: a gallium nitride substrate 11 having a principal surface 11a which makes an angle ?, in the range 40° to 50° or in the range more than 90° to 130°, with the reference plane Sc perpendicular to the reference axis Cx extending in the c axis direction; an n-type gallium nitride-based semiconductor layer 13; a second gallium nitride-based semiconductor layer 17; and a light-emitting layer 15 including a plurality of well layers of InGaN and a plurality of barrier layers 23 of a GaN-based semiconductor, wherein the direction of piezoelectric polarization of the plurality of well layers 21 is the direction from the n-type gallium nitride-based semiconductor layer 13 toward the second gallium nitride-based semiconductor layer 17.

Abstract: An optoelectronic component with short circuit protection is provided, comprising a first electrode layer (1) with a plurality of segments (11, 12), which are arranged separately from one another, a functional layer (2) on the first electrode layer (1), which emits electromagnetic radiation when in operation, a second electrode layer (3) on the functional layer (2), a power supply (4) and a plurality of electrical connections (51, 52). In each case at least one of the plurality of electrical connections (51, 52) is arranged between the first power supply (4) and at least one of the plurality of segments (11, 12) of the first electrode layer (1) for electrical contacting of the first electrode layer (1). The power supply (4) has a first cross-section and each of the plurality of electrical connections (51, 52) has a second cross-section. The second cross-section is smaller than the first cross-section, and the electrical connections (51, 52) take the form of fuses.