Abstract: A method and apparatus for variable rate compression with a conditional autoencoder is herein provided. According to one embodiment, a method includes training a conditional autoencoder using a Lagrange multiplier and training a neural network that includes the conditional autoencoder with mixed quantization bin sizes.

Abstract: In a particular implementation, a method of data conversion is disclosed. For example, for each word-line of a plurality of word-lines in a memory array, the method includes: 1) determining, by a digital comparator, if digital data exceeds a particular threshold, and 2) in response to the digital data determined to be above the threshold, transmitting, by the digital comparator, an output signal corresponding to the digital data to a digital-to-analog converter (DAC) device. Additionally, the DAC is configured to generate an analog signal.

Abstract: A method of compressing data is described in which the compressed data is generated by either or both of a primary compression unit or a reserve compression unit in order that a target compression threshold is satisfied. If a compressed data block generated by the primary compression unit satisfies the compression threshold, that block is output. However, if the compressed data block generated by the primary compression unit is too large, such that the compression threshold is not satisfied, a compressed data block generated by the reserve compression unit using a lossy compression technique, is output.

Abstract: Various embodiments of the present technology may comprise methods and apparatus for an analog-to-digital converter. Methods and apparatus for an analog-to-digital converter (ADC) may be configured as a delta-sigma type ADC and include an integrator circuit formed using two switched-capacitor (SC) circuits that share a single operational amplifier. The switched-capacitor circuits receive various control signals such that one SC circuit performs sampling while the other SC circuit simultaneously performs integration.

Abstract: An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to output a first digital value corresponding to an analog input voltage. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first current signal and the second current signal in the current domain, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values into a digital output voltage.

Abstract: A continuous time Delta-Sigma (CT-??) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-?? modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-?? modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.

Abstract: A Planar Inverted-F Antenna, PIFA, comprises a sheet of conductive material including first, second, third and fourth contiguous sections, the first and third sections extending orthogonally away from the second section and the fourth section extending away from the third section. The sections are folded relative to one another to define a volume with a heights of the second section, a width of the second section, and a depth of the third section extending away from the second section. A supporting pin and a feed pin extend from the second section along an outer edge. A supporting leg extends from either the third or fourth sections, the supporting leg lying outside the plane of the supporting pin to support the PIFA when mounted on a printed circuit board, while allowing components to at least partially occupy the volume under the PIFA.

Abstract: A digital filter and a method for filtering a pulse density modulation (PDM) signal are presented. The digital filter has a first filter circuit to receive an input signal with input values at successive time steps to provide a filtered input signal with filtered values at successive time steps. The digital filter does not require sample-rate or data format conversions. Also, the digital filter is area and power efficient when implemented in hardware. Optionally, the digital filter has a sigma-delta modulator including the quantiser, the sigma-delta modulator being used to receive the filtered input signal and to process the filtered input signal before and/or after being quantised by the quantiser. This digital filter does not require sample-rate or data format conversions. This digital filter is area and power efficient when implemented in hardware.

Abstract: Described are multi-band panel antennas which are configurable to have heavy-duty construction and which are fully IP67 waterproof. Suitable applications for the disclosed antennas include internet of things (IoT) gateway and IoT routers, HD video streaming, transportation, and remote monitoring applications. Additionally, the antennas can deliver MIMO coverage technology for worldwide 4G LTE bands at 698 to 960 MHz/1710 to 2170 MHz/2490 to 2690 MHz/3300 to 3600 MHz, Satellite Band, dual-band 2.4/5.8 GHz WiFi, and GNSS (GPS-GLONASS-BeiDou).

Abstract: Disclosed is a stochastic time-to-digital converter, which includes a first arbiter cell that compares a timing of a reference signal and a timing of an input signal based on a voltage selected by a first selection signal from among a first voltage or a second voltage and outputs a first comparison result, a second arbiter cell that compares the timing of the reference signal with the timing of the input signal based on a voltage selected by a second selection signal from among the first voltage or the second voltage and outputs a second comparison result, and a binary converter that calculates a phase difference between the reference signal and the input signal based on the first comparison result and the second comparison result.

Abstract: An apparatus includes a time-to-digital converter (TDC). The TDC includes a fine TDC (F-TDC) to generate a first output signal in a first range in response to a first signal and a second signal, and a coarse TDC (C-TDC) to generate a second output signal in a second range in response to the first signal and a delayed version of the second signal.

Abstract: A system includes a first sensed voltage generated as a product of the first voltage reference and an unknown scalar, a second sensed voltage generated as a product of the first voltage reference and a known scalar, and an amplifier having gain error that generates a second voltage reference (first voltage reference or scaled version thereof). An ADC uses the second voltage reference to generate first and second digital values, representing the first and second sensed voltages, that contain error caused by the second voltage reference gain error. A processor uses the known scalar and a ratio based on the first and second digital values to remove the error from the first digital value. The first sensed voltage may be generated by pumping a current into a variable resistance sensor (VRS) whose resistance varies with respect to a time-varying stimulus (e.g., temperature) and is proportional to the unknown scalar.

Abstract: A DAC (60) is disclosed. It comprises an input port comprising N input terminals p1, p2, . . . , pN configured to receive voltages representing N input bits b1, b2, . . . , bN, respectively, wherein the significance of bj is higher than for bj?1 for j=2, 3, . . . , N. Furthermore, it comprises a capacitor ladder circuit (100) comprising N capacitors C1, C2, . . . , CN with capacitance C, each having a first terminal and a second terminal. Capacitor Cj is connected with its first terminal to the terminal pj of the input port. For each j=1, 2, . . . , N?1, the capacitor ladder circuit (100) comprises a capacitor (150j) with capacitance xC connected between the second terminal of capacitor Cj and the second terminal of capacitor Cj+1. The DAC (60) also comprises an input circuit (140) connected to the input port comprising at least one capacitor (1601-160N), each connected between a unique one of the input terminals p1, p2, . . . , pN of the input port and signal ground.

Abstract: A current digital-to-analog converter includes a binary current-generating section configured to generate a binary-weighted current based on a first set of control signals; a unary current-generating section configured to generate a unary-weighted current based on a second set of control signals; and a current combining circuit configured to add or subtract a reference current and a current generated by a current source of the unary current-generating section using the binary-weighted current.

Abstract: A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADCs, an open-loop clocking circuit, and a time-multiplexing circuit. The plurality of ADCs receive an analog input signal. Each ADC is configured to sample the analog input signal upon receipt of a respective clock signal. The open-loop clocking circuit receives a main clock signal having a reference frequency, and then divides the main clock signal into a sequential plurality of respective clock signals, each having a frequency lower than the reference frequency, and each triggered by one other respective clock signal starting from the main clock signal. The open-loop clocking circuit then distributes the plurality of respective clock signals to the plurality of ADCs. The time-multiplexing circuit is coupled to the plurality of ADCs and is configured to combine respective digital output signals from the plurality of ADCs into a time series.

Abstract: Analog-to-digital converter (ADC) circuitry to convert an analog signal to a digital signal is disclosed herein. The ADC circuitry can utilize pipelined-interpolation analog-to-digital converters (PIADCs) with adaptation circuitry to correct regenerative amplification cells of the PIADCs. The PIADCs can implement a rotational shuffling scheme for correction of the regenerative amplification cells, where the correction implemented by the regenerative amplification cells allows for offsetting of latches of the regenerative amplification cells.

Abstract: Described herein is a ?? modulator with improved metastability in which the control loop remains stable. In one embodiment, the ?? modulator utilizes differently delayed feedback to successive integrators of the control loop to suppress metastability errors without compromising the stability of the control loop. This is accomplished by including one or more quantizers in the control loop. This technique may be applied to control loops of at least second order, i.e., having two or more integrator stages, where at least one feedback term after the first is non-zero.

Abstract: A circuit includes a first transistor and a second transistor having respective control terminals coupled to receive first and second bias voltages. A first electronic switch is coupled in series with, and between current paths of the first and second transistors to provide an output current line between a circuit output node and ground. A second electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between a bias node and a charge transfer node in the output current line. A third electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between the charge transfer node and the control terminal of the second transistor.

Abstract: Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta sigma loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.

Abstract: Various embodiments are provided for length-limited Huffman encoding in a data compression accelerator in a computing environment by a processor. Symbol counts of a plurality of symbols in compressed data may be normalized and manipulated according to a maximum code length limiting operation such that those of the plurality of symbols having a least frequent symbol count have a symbol count equal to a maximum code length of a Huffman tree.