Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The processor receives a compression request which designates data represented by a plurality of integers, and reduces entropy by multiplying a data matrix, which is obtained by representing the data designated by the compression request by a matrix, by a transformation matrix of which determinant is 1.

Abstract: A device includes a comparator configured to compare a transmission phase of light in a photonic component with a reference phase. The device further includes a heater configured to control a temperature of the photonic component. The heater includes a plurality of heater segments, and a plurality of switches, wherein each switch of the plurality of switches is between a pair of heater segments of the plurality of heater segments. The device further includes a controller configured to control operation of each switch of the plurality of switches based on results from the comparator for selectively connecting heater segments of the plurality of heater segments in series.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, an electronic device includes a plurality of input ports configured to receive at least two serial communication signals, an encoder circuit configured to encode the at least two serial communication signals based on signal edges of the at least two serial communication signals to generate an encoded serial communication signal, the encoded serial communication signal enabling reconstruction of the at least two serial communication signals independent of a clock signal, and a transmitter configured to transmit the encoded serial communication signal.

Abstract: This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

Abstract: Multi-Nyquist differentiator circuits and a radio frequency sampling receiver that applies a multi-Nyquist differentiator circuit. A multi-Nyquist differentiator includes a fixed coefficient filter, a scaling circuit, and a summation circuit. The fixed coefficient filter is configured to filter digital samples generated by an ADC. The scaling circuit is coupled to an output of the fixed coefficient filter, and is configured to scale output of the fixed coefficient filter based on a selected Nyquist band. The summation circuit is coupled to the scaling circuit, and is configured to generate a derivative of the digital samples based on output of the scaling circuit.

Abstract: The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.

Abstract: A two-step, hybrid analog-to-digital converter (ADC) includes a Delta-Sigma ADC that employs chopping to resolve MSBs, a Nyquist ADC that employs correlated double sampling (CDS) to resolve LSBs, and a combiner that combines the MSBs and the LSBs to generate a digital output signal. The Delta-Sigma ADC has first and second integrators where, after resolving the MSBs, the first integrator is re-configured to function as a reference buffer for the Nyquist ADC and the second integrator is re-configured to function as the Nyquist ADC.

Abstract: In one embodiment, a multi-beam antenna is described. The multi-beam antenna includes a reflector having a single reflector surface defining a first focal region and a second focal region. A first feed group is located within the first focal region. The first feed group includes a first feed oriented relative to the reflector define a first beam pointed in a first direction. The multi-beam antenna further includes a fixed attachment mechanism attaching the first feed group to the reflector such that a position of the first feed group is fixed relative to the reflector. The multi-beam antenna further includes a second feed group located within the second focal region. The second feed group includes a second feed oriented relative to the reflector to define a second beam pointed in a second direction.

Abstract: An analog-to-digital converter circuit comprises code-shuffling circuitry, a plurality of digital-to-analog converter circuits, a plurality of difference circuits, and a plurality of latch circuits. The code-shuffling circuitry is operable to shuffle a plurality of digital codes among a plurality of its outputs. The plurality of digital-to-analog converter circuits are operable to convert a digital code on the respective one of the outputs to a corresponding one of a plurality of analog reference voltages. The plurality of difference circuits is operable to generate a respective one of a plurality of difference signals corresponding to a difference between an input voltage and a respective one of the plurality of reference voltages. The plurality of latch circuits is operable to latch a respective one of the plurality of difference signals to a corresponding one of a plurality of digital values.

Abstract: In general, embodiments of the present invention provide systems, methods and computer readable media for data record compression using graph-based techniques.

Abstract: Facilitating a reduction in sensor system latency, circuit size, and current draw utilizing a group of continuous-time Nyquist rate analog-to-digital converters (ADCs) in a round-robin manner is presented herein. A sensor system can comprise a group of sensors that generate respective sensor output signals based on an external excitation of the sensor system; a multiplexer that facilitates a selection, based on a sensor selection input, of a sensor output signal of the respective sensor output signals corresponding to a sensor of the group of sensors; a sense amplifier comprising a charge or voltage sensing circuit that converts the sensor output signal to an analog output signal; and a continuous-time Nyquist rate analog-to-digital converter of the group of continuous-time Nyquist rate ADCs that converts the analog output signal to a digital output signal representing at least a portion of the external excitation of the sensor system.

Abstract: An apparatus including an antenna; a first part including a first ground plane portion; a second part including a second ground plane portion; a first electrical connection between the first part and a second part; and a second electrical connection between the first ground plane portion and the second ground plane portion that includes a reactive component.

Abstract: Systems, methods, and computer-readable media are described for performing data compression in a manner that does not require software to make a call to hardware to close a compressed data block, thereby reducing computational overhead. In response to a request from software to data compression hardware for a data encoding, the hardware may return the data encoding as well as an end-of-block symbol encoding value and bit length. The hardware may load the end-of-block symbol encoding value and bit length into a different area in the returned structure such that the software has direct access to the value. When the software determines that a block should be closed, the software may retrieve the end-of-block symbol and insert it into the block without needing to make a call to hardware. The software may then make a call to the hardware to request a new data encoding for subsequent compressed data blocks.

Abstract: A compression system includes an encoder and a decoder. The encoder can be deployed by a sender system to encode a tensor for transmission to a receiver system, and the decoder can be deployed by the receiver system to decode and reconstruct the encoded tensor. The encoder receives a tensor for compression. The encoder also receives a quantization mask and probability data associated with the tensor. Each element of the tensor is quantized using an alphabet size allocated to that element by the quantization mask data. The encoder compresses the tensor by entropy coding each element using the probability data and alphabet size associated with the element. The decoder receives the quantization mask data, the probability data, and the compressed tensor data. The quantization mask and probabilities are used to entropy decode and subsequently reconstruct the tensor.

Abstract: Methods of encoding and decoding data in which some data symbols are entropy coded and some data symbols are bypass coded. The encoder separates the coded symbols into an entropy coded stream and a bypass coded stream. The streams are packaged in a data unit that has a payload structured to contain one of the streams in forward order and the other stream in reverse order, with the reverse order stream aligned with the end of the data unit. In this manner, at the decoder, the decoder may begin decoding the forward order stream from its beginning and may also begin decoding the reverse order stream from its beginning at the end of the data unit by extracting symbols in reverse order. The data unit does not need to signal the length of the streams. The decoder determines the length of the data unit from explicit or implicit signaling.

Abstract: A technique for processing streams of time-varying data provides first through Nth processing stages, each processing stage having a respective encoder and a respective decoder. The encoder of each processing stage receives successive values of time-varying input data and generates therefrom encoded output data. Each encoder provides its encoded output data as input to its respective decoder, which generates a prediction of a next value of the time-varying input data that the encoder will receive. Each encoded output is based upon both (1) a current input value and (2) one or more previous input values, such that encodings are based at least in part on history. Encoders are coupled output-to-input, with the input of the first encoder receiving an overall processing input. Decoders are likewise coupled output-to-input, with each decoder providing feedback to the previous decoder and the first decoder providing an overall processing output.

Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.

Abstract: A delta-sigma modulator and a delta-sigma converter include an analog amplifying unit to amplify an analog signal and having at least a primary feedback coefficient, a quantizer to quantize an output signal of the analog amplifying unit, a DA converter to perform DA conversion on output of the quantizer and output a feedback signal, an adder-subtractor to input into the analog amplifying unit an analog signal obtained by subtracting the feedback signal from an analog signal input therein, a reset circuit to reset the analog amplifying unit at predetermined periods, and a control circuit to control the analog amplifying unit so that the analog amplifying unit operates as an integrator with the primary feedback coefficient of 1 until a predetermined period elapses after the reset circuit resets the analog amplifying unit and as an amplifier with the primary feedback coefficient of greater than one after the predetermined period has elapsed.

Abstract: Systems and methods are provided for improved linearity of audio amplifiers. In one example, a system includes a first current source configured to provide a first current signal having a first current source output capacitance, and a second current source configured to provide a second current signal having a second current source output capacitance, where the first and second current source output capacitances are a different value. The system further includes a first capacitor compensation device coupled to an output of the first current source configured to provide a capacitance value to compensate for the second current source output capacitance, and a second capacitor compensation device coupled to an output of the second current source configured to provide a capacitance value to compensate for the first current source output capacitance. The system further includes a plurality of switches configured to switch the first and second current signals.

Abstract: A circuit includes a first integration stage, a quantizer, a second integration stage coupled between the first integration stage and the quantizer, and a digital-to-analog converter (DAC). The first integration stage includes a first input node pair configured to receive a pair of differential analog input signals, and the quantizer is configured to generate a digital signal based on the pair of differential analog input signals and a clock signal. The second integration stage includes a second input node pair, and the DAC is configured to receive the digital signal and output feedback signals to at least one input node pair of the first input node pair or the second input node pair.