Abstract: An integrated circuit includes: a first differential buffer suitable for receiving a primary signal through a primary input terminal thereof, and receiving a secondary signal through a secondary input terminal thereof, wherein the secondary signal has a phase opposite to a phase of the primary signal; a second differential buffer suitable for receiving a first reference voltage through primary and secondary input terminals thereof; and an operational amplifier suitable for receiving a first common mode voltage of the primary and secondary output terminals of the first differential buffer and a second common mode voltage of the primary and secondary output terminals of the second differential buffer, to output the first reference voltage.

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

Abstract: A method of compression is disclosed in which an input sequence of bits is divided into a plurality of portions. Each portion is sub-divided into a plurality of sub-divisions. Frequency analysis is performed to determine the number of occurrences of each sub-division permutation and a processed sequence of bits is generated based on the frequency analysis. The processed sequence of bits includes extraction information for use in reconstructing said input sequence of bits from said processed sequence of bits. The extraction information comprises sub-division order information identifying an ordered sequence comprising each possible sub-division permutation arranged in order of how many times, within said input sequence of bits, a portion comprises a sub-division having bits arranged in that possible sub-division permutation.

Abstract: A photonic feedforward analog-to-digital converter (ADC) is provided. According to one aspect of the invention, the signal to be digitized is applied to only one electro-optic modulator. High speed is achieved by taking advantage of the fundamental property of a Pockels Cell to control wave polarization using the electro-optic effect. In a further aspect, once a bit is determined, its state is fed forward to the next least significant bit to aid in determination of the next lower bit. This nonlinear feedforward aspect of the ADC provides simplicity of its architecture.

Abstract: An active antenna for UHF/VHF signal receiving is described, the active antenna being capable of configuration in one of a plurality of possible modes. The active antenna includes an antenna element configured for multiple resonances in the UHF/VHF bands, and capable of generating multiple radiation modes as well as active impedance matching using a microprocessor and multi-port switch having variable or multiple selectable modes. The active antenna may include a second antenna element arranged in a right-angle orientation with respect to the first antenna element. The first antenna element, second antenna element, or a combination may be selected for receiving signals in at a desired frequency. A three-dimensional antenna assembly is also described. Each of the examples illustrate an active beam steering antenna capable of UHF/VHF signal receiving.

Abstract: It is described an electronic device (1) for measuring an electric quantity, comprising: an analog-digital conversion module (2) configured to digitally convert time portions of an analog signal (SM(t)) to be measured alternated with time portions of a reference analog signal (SR(t)), for supplying respective first (DSM) and second pluralities (DSR) of digital values and a digital processing module (3) configured to: calculate a first mean amplitude (A1) of the first pluralities of digital values, and a second mean amplitude (A2) of the second pluralities of digital values; the first and second mean amplitudes being proportional to a mean gain value of the analog-digital conversion module (2); supply a ratio value (VRT) of the first mean amplitude to the second mean amplitude, representative of a measured amplitude of the analog signal (SM(t)) to be measured.

Abstract: A digital-to-analog converter comprises a converter output (11), a dummy output (12), a first number N of current sources (13-17), a first switching arrangement (18), a first current divider (24), a second switching arrangement (31) and a second current divider (60). The current sources (13-17) are coupled via the first switching arrangement (18) to the converter output (11), the dummy output (12) or to an input current terminal (25) of the first current divider (24). The output current terminals (26-30) of the first current divider (24) are coupled via the second switching arrangement (31) to the converter output (11), the dummy output (12) or to an input current terminal (61) of the second current divider (60). The output current terminals (63-66) of the second current divider (60) are coupled to the converter output (11) or the dummy output (12).

Abstract: A circuit includes a first transistor and a second transistor having respective control terminals coupled to receive first and second bias voltages. A first electronic switch is coupled in series with, and between current paths of the first and second transistors to provide an output current line between a circuit output node and ground. A second electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between a bias node and a charge transfer node in the output current line. A third electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between the charge transfer node and the control terminal of the second transistor.

Abstract: A power conversion apparatus can include: a power module configured to transfer an analog sensing signal corresponding to a current of an inductor and a voltage applied at both terminals of a capacitor, and to perform power conversion by driving a power semiconductor with a pulse-width modulation signal; and a controller configured to receive the analog sensing signal from the power module, to convert the analog sensing signal to a digital signal, to generate the pulse-width modulation signal, and to transfer the pulse-width modulation signal to the power module.

Abstract: The disclosure relates to a glass-based antenna array package. In an aspect, such a glass-based antenna array package includes a single glass substrate layer, one or more antennas attached to a first side of the glass substrate layer, at least one semiconductor device attached to a second side of the glass substrate layer, and a first photoimageable dielectric layer adhered to the second side of the glass substrate layer and encapsulating the at least one semiconductor device. A method of manufacturing the same is also disclosed.

Abstract: An antenna device including an antenna radiator and a feed line layer is provided. The antenna radiator is disposed on a first surface of a detachable substrate. The antenna radiator receives a microwave signal of at least one frequency band. The feed line layer is disposed on a second surface of a control circuit board. The feed line layer includes a signal feed line. The signal feed line is coupled to the antenna radiator through a connection point. The connection point is located on one side of the control circuit board. The detachable substrate and the control circuit board are arranged to have an angle between the first surface and the second surface. In addition, an electronic apparatus is also provided.

Abstract: A system for digitizing a sampled input value includes a digital-to-analog converter for generating an output signal as a function of (1) the sampled input value, (2) a reference value, and (3) digital codes, and a multi-bit analog-to-digital converter for determining the digital codes in first, intermediate, and subsequent cycles. Dither is dynamically added to the digital-to-analog converter in the intermediate cycle. The dither is corrected for in the subsequent cycle.

Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.

Abstract: An integrated circuit is described. The integrated circuit comprises a first portion having programmable resources; a second portion having hardened circuits including an analog-to-digital converter circuit configured to receive an input signal and generate an output signal; and a monitor circuit configured to receive an output signal generated by the analog-to-digital converter circuit; wherein the monitor circuit is configurable to control a calibration of the analog-to-digital converter circuit based upon signal characteristics of the output signal generated by the analog-to-digital converter circuit. A method of receiving data in an integrated circuit is also described.

Abstract: Integrator circuits comprising switched capacitors, non-switched capacitors, and an op amp. One embodiment is directed to an integrator circuit comprising an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output, a first sampling capacitor and a first feedback capacitor, and a first non-switched capacitor. The first feedback capacitor is coupled between the inverting input and the non-inverting output of the op amp, and the first non-switched capacitor is coupled between the negative integrator input and the inverting input of the op amp. During a sampling phase, a positive integrator input is coupled to the first sampling capacitor, and during an integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.

Abstract: Multilevel leaky-mode optical elements, including reflectors, polarizers, and beamsplitters. Some of the elements have a plurality of spatially modulated periodic layers coupled to a substrate. For infrared applications, the optical elements may have a bandwidth larger than 600 nanometers.

Abstract: A flash analog to digital converter (ADC) includes a first, second, and third double data rate comparator core configured to determine a relative voltage of a first differential input signal during each of a rising edge and a falling edge in a single clock cycle of a comparator clock input to the comparator core. An inverted comparator clock coupled to the third comparator core reduces kickback noise. The ADC includes a first and a second floating voltage reference configured to shift a voltage of a differential comparator input by a fixed amount, and produce the first and second differential input signal. The third comparator core is cross coupled between the first and second comparator core.

Abstract: A spacecraft includes an antenna reflector coupled with an antenna pointing mechanism (APM), a beam forming network including variable amplitude and phase (VAP) adjusting arrangements, a tracking feed that receives a beacon signal by way of the reflector, and an autotrack receiver that measures pointing errors of the reflector from the received beacon signal and outputs corresponding pointing errors to the APM controller and to a VAP element controller. The antenna reflector is illuminated by radiating feed elements configured as a phased array that produces, in a far field of the reflector, a set of user beams. The APM controller causes the APM to adjust the reflector pointing, at a frequency less than f1, to reduce the measured pointing errors. The VAP element controller adjusts pointing of the user beams by adjusting beam forming coefficients of the VAP adjusting arrangements at a second frequency greater than f1.

Abstract: A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.

Abstract: Continuous-time pipeline analog-to-digital converters can achieve excellent performance, and avoid sampling-related artifacts traditionally associated with discrete-time pipeline ADCs. However, the continuous-time circuitry in the ADCs can pose a challenge for digital signal reconstruction, since the transfer characteristics of the continuous-time circuitry are not as well characterized or as simple as their discrete-time counterparts. To achieve perfect digital signal reconstruction, special techniques are used to implement an effective and efficient digital filter that combines the digital output signals from the stages of the CT ADCs.