Patents Examined by Huan Hoang
  • Patent number: 10783951
    Abstract: Apparatuses and methods are disclosed that include two transistor-one capacitor memory and for accessing such memory. An example apparatus includes a capacitor coupled to first and second selection components. The apparatus further includes a first digit line and the first selection component configured to couple a first plate of the capacitor to the first digit line, and also includes a second digit line and the second selection component configured to couple the second plate to the second digit line. A sense amplifier is coupled to the second digit line and is configured to amplify a voltage difference between a voltage coupled to the second digit line and the reference voltage.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Christopher J. Kawamura, Scott J. Derner
  • Patent number: 10783982
    Abstract: A data storage system can receive a data write request to write data to a physical address of a non-volatile semiconductor memory prior to detecting an error while storing the write data to the physical address. The detected error is corrected with a monitor module connected to the non-volatile semiconductor memory and a counter associated with the physical address is incremented with the monitor module in response to the corrected error. The write data can be subsequently read to a host in response to a data read request.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 22, 2020
    Assignee: Seagate Technology LLC
    Inventor: Stephen H. Perlmutter
  • Patent number: 10783943
    Abstract: A STT-MRAM comprises apparatus, a method of operating and a method of manufacturing a self-referenced magnetoresistive memory and a plurality of magnetoresistive memory element including a self-referenced read scheme through a write/read circuitry coupled to the bit line positioned adjacent to selected ones of the plurality of magnetoresistive memory elements to supply bi-directional spin-transfer recording and reading currents across the MTJ stack. Thus magnetization of a recording layer can be readily switched or reversed to the direction in accordance with a direction of a current across the MTJ stack by applying a spin transfer current, and the magnetization of a reference layer can be readily rotated to two reading directions subsequently in accordance with directions of currents across the MTJ stack by applying low spin transfer currents.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: September 22, 2020
    Inventor: Yimin Guo
  • Patent number: 10778196
    Abstract: Embodiments of the present disclosure pertain to reducing power consumption in a processor circuit. In one embodiment, a processor circuit comprises a plurality of data storage modules. The plurality of data storage modules each include one or more first multibit flip flop circuits having a first power consumption per bit and one or more second flip flop circuits having a second power consumption per bit. The first multibit flip flop circuits may have more bits than the second flip flop circuits. Additionally, the first power consumption per bit may be less than the second power consumption per bit such that power consumption is reduced when the first multibit flip flop circuits are used to store bits that change with a higher frequency than bits stored in the second flip flop circuits.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 15, 2020
    Assignee: Groq, Inc.
    Inventor: Sushma Honnavara-Prasad
  • Patent number: 10777281
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first group of conductive materials interleaved with a first group of dielectric materials, a first pillar extending through the first group of conductive materials and the first group of dielectric materials, memory cells located along the first pillar, a conductive contact coupled to one of the conductive materials, and a second pillar extending through a second group of conductive materials and a second group of dielectric materials. The second pillar includes a first portion coupled to a conductive region, a second portion, and a third portion, and a fourth portion coupled to the conductive contact. The second portion is located between the first and third portions. The second portion has a doping concentration less than a doping concentration of each of the first and fourth portions.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Guangyu Huang, Haitao Liu, Akira Goda
  • Patent number: 10777259
    Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for convolution computation. One example apparatus generally includes a static random-access memory (SRAM) having a plurality of memory cells. Each of the plurality of memory cells may include a flip-flop (FF) having an output node and a complementary output node; a first switch coupled between the output node and a bit line (BL) of the SRAM, the first switch having a control input coupled to a word line (WL) of the SRAM; and a second switch coupled between the complementary output node and a complementary bit line (BLB) of the SRAM, the second switch having another control input coupled to a complementary word line (WLB) of the SRAM.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 15, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Zhongze Wang, Xiaochun Zhu
  • Patent number: 10770128
    Abstract: A refreshing method is described. The method includes recognizing a set of blocks of a non-volatile memory for refreshing and then refreshing a subset of the data within the blocks, where, invalid data within the blocks is not recognized for refreshing and a group of blocks whose oldest data has not aged for a pre-set time period is not recognized for refreshing.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 8, 2020
    Assignee: Intel Corporation
    Inventors: Mark Anthony Golez, David J. Pelster, Xin Guo, Paul D. Ruby
  • Patent number: 10770431
    Abstract: The present disclosure generally relates to storage devices comprising a memory device having a layout optimized for data failure protection. A storage device comprises a memory device having a first package and a second package disposed adjacent to the first package. The first package comprises an even number of memory die having a first storage capacity, and the second package comprises two memory die having a second storage capacity. A first half of the memory dies of the first package and a first memory die of the second package are coupled to a first channel. A second half of the memory dies of the first package and a second memory die of the second package are coupled to a second channel parallel to the first channel.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: September 8, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Daniel L. Helmick, Kent Anderson
  • Patent number: 10770124
    Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 8, 2020
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
  • Patent number: 10762934
    Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to write electronic data into one or more memory cells in a write mode of operation and/or to read the electronic data from the one or more memory cells in a read mode of operation. The various exemplary memory storage devices can select various control lines to read the electronic data from the one or more memory cells onto data lines and/or to write the electronic data from these data lines into the one or more memory cells. In some situations, these data lines are charged, also referred to as pre-charged, to a first logical value, such as a logical one, before the various exemplary memory storage devices write the electronic data into the one or more memory cells. During this pre-charging of these data lines, the various exemplary memory storage devices electrically isolate these data lines from specialized circuitry within these exemplary memory storage devices.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Chi Wu, Cheng Hung Lee, Chien-Kuo Su, Chiting Cheng, Yu-Hao Hsu, Yangsyu Lin
  • Patent number: 10762960
    Abstract: A memory architecture includes: a plurality of cell arrays each of which comprises a plurality of bit cells, wherein each of bit cells of the plurality of cell arrays uses a respective variable resistance dielectric layer to transition between first and second logic states; and a control logic circuit, coupled to the plurality of cell arrays, and configured to cause a first information bit to be written into respective bit cells of a pair of cell arrays as an original logic state of the first information bit and a logically complementary logic state of the first information bit, wherein the respective variable resistance dielectric layers are formed by using a same recipe of deposition equipment and have different diameters.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Der Chih, Chung-Cheng Chou, Wen-Ting Chu
  • Patent number: 10762939
    Abstract: Computer memory technology is disclosed. In one example, a method for isolating computer memory blocks in a memory array from one another can include forming an opening between adjacent blocks of memory structures. The method can also include forming a protective liner layer on at least the memory structures. The method can further include disposing isolating material in the opening and on the protective liner layer. The method can even further include removing the isolating material on the protective liner layer. The method can additionally include removing the protective liner layer on the memory structures. Associated devices and systems are also disclosed.
    Type: Grant
    Filed: July 1, 2017
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Christopher J. Larsen, David A. Daycock, Qian Tao, Saniya Rathod, Devesh K. Datta, Srivardhan Gowda, Rithu K. Bhonsle
  • Patent number: 10755756
    Abstract: Apparatuses and methods for creating a constant DQS-DQ delay in a memory device are described. An example apparatus includes a first adjustable delay line configured to provide a delay corresponding to a loop delay of a data strobe signal pathway internal to a memory, a second adjustable delay line included in the internal data strobe signal pathway, and a timing control circuit coupled to the first and second adjustable delay lines and configured to adjust a delay of the second adjustable delay line responsive to output from the first adjustable delay line and the data strobe signal pathway.
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: August 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yantao Ma, Huy T. Vo
  • Patent number: 10748602
    Abstract: One embodiment provides an apparatus. The apparatus includes a pair of nonvolatile resistive random access memory (RRAM) memory cells coupled to a volatile static RAM (SRAM) memory cell. The pair of nonvolatile RRAM memory cells includes a first RRAM memory cell and a second RRAM memory cell. The first RRAM memory cell includes a first resistive memory element coupled to a first bit line, and a first selector transistor coupled between the first resistive memory element and a first output node of the volatile SRAM memory cell. The second RRAM memory cell includes a second resistive memory element coupled to a second bit line, and a second selector transistor coupled between the second resistive memory element and a second output node of the volatile SRAM memory cell.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Huichu Liu, Sasikanth Manipatruni, Daniel H. Morris, Kaushik Vaidyanathan, Niloy Mukherjee, Dmitri E. Nikonov, Ian Young, Tanay Karnik
  • Patent number: 10748631
    Abstract: A semiconductor memory device includes a memory string with a first selection transistor, a first memory cell, a second memory cell, and a second selection transistor connected in series. A first word line connects to the first memory cell, and a second word line connects to the second memory cell. Selection gates line are connected to first and second selection transistors. A control circuit is configured to control a write operation on the first memory string. The write operation includes a program loop with a program operation and a program verification operation. After the program loop is completed, a first voltage is applied to the first and second word lines and a second voltage is applied to the selection gate lines. The first voltage is sufficient to turn on the first and second memory cells. The second voltage is sufficient to turn on the selection transistors.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: August 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Tsubouchi
  • Patent number: 10741232
    Abstract: A memory device comprising a memory array of a plurality of memory bit cells; a read reference system comprising four or more reference memory bit cells in a reference column of the memory array; wherein a first bit cell of the reference memory bit cells is always selected; wherein a bitline of the first bit cell of the reference memory bit cells is connected to a bitline of a first subset of the reference memory bit cells, and a select line of the first bit cell of the reference memory bit cells is connected to a reference select signal; wherein a select line of each of the first subset of the reference memory bit cells and a second subset of the reference memory bit cells are coupled together; and wherein a bitline blref of the second subset of the reference memory bit cells outputs a read reference signal.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kotb Jabeur, John Kenneth DeBrosse
  • Patent number: 10741242
    Abstract: Memory devices are provided. A memory device includes a voltage generation circuit that includes an offset compensator configured to receive a reference voltage and an offset code and to link the offset code to the reference voltage. The voltage generation circuit includes a comparator configured to compare the reference voltage linked to the offset code with a bit line pre-charge voltage and to output driving control signals. The voltage generation circuit includes a driver configured to output the bit line pre-charge voltage at a target level of the reference voltage in response to the driving control signals. The voltage generation circuit includes a background calibration circuit configured to generate the offset code for performing control so that a target short current flows through an output node of the driver from which the bit line pre-charge voltage is output. Related methods of generating a bit line pre-charge voltage are also provided.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: August 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-hun Seo, Seung-hyun Cho, Chang-ho Shin, Yong-jae Lee
  • Patent number: 10734055
    Abstract: A memory device according to an embodiment includes: a plurality of memory cells including a storage element having a first and second terminals; a reference resistor having a third and fourth terminals; a first current source electrically connected to the first terminal of the storage element in the selected memory cell; a second current source electrically connected to the third terminal; and a determination circuit that determines the greater one among a resistance value of a storage element of selected one and a resistance value of the reference resistor, the resistance value of the reference resistor being smaller than a middle value between a mean value of first resistance values obtained from the storage elements in the high-resistance state and a mean value of second resistance values obtained from the storage elements in the low-resistance state, and greater than the mean value of the second resistance values.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: August 4, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Sugiyama, Naoharu Shimomura, Kazutaka Ikegami
  • Patent number: 10734085
    Abstract: There are provided a memory device and an operating method thereof. A memory device includes: a peripheral circuit for decreasing threshold voltages of memory cells included in a selected memory block and then performing an erase verify operation for detecting a threshold voltage distribution of the memory cells, wherein the peripheral circuit applies an erase pulse to a well, bit lines or source line in which the selected memory block is included a preset number of times; and a control logic for outputting a voltage setup code according to the threshold voltage distribution of an erase status, which is detected by the erase verify operation.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventor: Dong Hun Lee
  • Patent number: 10734078
    Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-Sang Lee