Abstract: Devices, circuits, and methods are provided. A circuit comprises a tracking word line circuit that is configured to receive an internal clock signal, a turbo signal, and a read enable signal, and to generate a first tracking reading signal and a first tracking writing signal in response to the internal clock signal the turbo signal, and the write enable signal. The circuit also comprises a tracking bit line circuit configured to receive the first tracking reading signal and the first tracking writing signal, wherein the tracking bit line circuit is configured to generate a tracking bit line signal in response to the first tracking reading signal and the first tracking writing signal, wherein the tracking word line circuit is configured to generate a reset signal in response to the tracking bit line signal and transmit the reset signal to the clock generator.

Abstract: An SRAM cell includes a first pass gate transistor connected with a first word-line and a local bit-line, a first inverter that includes an output terminal connected with the first pass gate transistor and an input terminal, a second inverter that includes an input terminal connected with the first pass gate transistor and an output terminal, a second pass gate transistor connected with a second word line, the input terminal of the first inverter and the output terminal of the second inverter, and a complementary local bit-line, a first transistor connected with the second pass gate transistor, a local computing line, and a ground electrode, and a second transistor connected with a third word-line, the local computing line, and the ground electrode.

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

Abstract: One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first memory cell coupled between a first local select line and a first local bit line, a second memory cell coupled between a second local select line and a second local bit line, a first switch coupled to a global bit line, a second switch coupled between the first local bit line and the first switch, and a third switch coupled between the second local select line and the first switch.

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

Abstract: A sensing amplifier circuit includes first and second P-type transistors and first and second N-type transistors. The first P-type transistor includes a gate coupled to an input node, a source and a bulk coupled to a first node, and a drain coupled to an output node. The second P-type transistor includes a gate coupled to an inverted reading-triggered signal, a source coupled to a voltage source, and a drain coupled to the first node. The first N-type transistor includes a gate coupled to the input node, a drain coupled to the output node, and a source coupled to ground. The second N-type transistor includes a gate receiving the inverted reading-triggered signal, a drain coupled to the output node, and a source coupled to the ground. The first P-type transistor includes an N-type well region that is electrically connected to the source and bulk of the first P-type transistor.

Abstract: A storage device including a non-volatile memory for storing data, a temperature sensor having resistance that changes according to temperature of the temperature sensor, and a temperature measurement circuit including a plurality of transistors, which are turned on or off based on a current of the temperature sensor and have different threshold voltages from one another. The temperature management circuit may be configured to apply a current to the temperature sensor and generate information indicating the temperature of the temperature sensor or indicating damage to the temperature sensor based on an output current obtained from the plurality of transistors.

Abstract: Provided is a memory device with a vertical channel structure. The memory device includes a memory cell array including a plurality of memory cells and a plurality of string selection lines, a negative charge pump configured to generate a bias voltage of a negative level, to be applied to at least one of the plurality of string selection lines, and a control logic circuit configured to apply, for a first period, a prepulse voltage to at least one unselected string selection line among the plurality of string selection lines excluding a selected string selection line to which a memory cell selected from among the plurality of memory cells is connected and thereafter apply the bias voltage to the at least one unselected string selection line so as to perform a read operation on the selected memory cell.

Abstract: A Content-Addressable Memory (CAM) is disclosed in which a single lookup request is split into several iterations, with each iteration having a partial lookup. Results of the partial lookups are incrementally accumulated to obtain a final lookup result. The incremental CAM lookup allows for smaller CAM hardware to be used than typically needed for a similar size lookup, which saves area and power over prior approaches. In one embodiment, a memory is used in conjunction with a CAM and the CAM is configured on each partial lookup using a read from the memory. Accumulation logic can then be used to logically combine the results of the partial lookups.

Abstract: Control logic in a memory device receives a request to perform a memory access operation on a memory array of the memory device and determines an operating temperature of the memory device. The control logic further modifies a default magnitude of a source voltage signal based on the operating temperature to a form a modified source voltage signal, causes the modified source voltage signal to be applied to the memory array, and performs the memory access operation on the memory array.

Abstract: A read-modify-write operation is performed, within a single cycle of a clock signal, by: decoding an address to select a word line of a memory; applying a word line signal at a first voltage level to the selected word line; reading a current data word from a data word location in the memory; reducing the word line signal from the first voltage level to the second voltage level; performing a mathematical modify operation internally within the memory on the current data word to generate a modified data word; increasing the word line signal from the second voltage level to the first voltage level; and writing the modified data word back to the location in the memory.

Abstract: There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.

Abstract: Methods, systems, and devices for link evaluation for a memory device are described. A memory device may receive signaling over a channel and may identify logic values encoded into the signaling based on sampling the signaling against a reference voltage. The sampling may occur at a reference time within a sampling period. To evaluate a quality (e.g., margin of error) of the channel, the memory device may adjust the reference voltage, the reference time, or both, and either the memory device or the host device may determine whether the memory device is still able to correctly identify logic values encoded into signaling over the channel. In some cases, the channel quality may be evaluated during a refresh cycle or at another opportunistic time for the memory device.

Abstract: Control logic in a memory device determines to initiate a string read operation on a first memory string of a plurality of memory strings in a block of a memory array, the block comprising a plurality of wordlines, wherein the first memory string is designated as a sacrificial string. The control logic further causes a read voltage to be applied to each of the plurality of wordlines concurrently and senses a level of current flowing through the sacrificial string while the read voltage is applied. In addition, the control logic identifies, based on the level of current flowing through the sacrificial string, whether a threshold level of read disturb has occurred on the block.

Abstract: An aging monitoring circuit of a semiconductor memory device includes a threshold voltage sensing part including an aging monitoring transistor, enabled in response to activation of an aging monitoring signal, and generating a sensing threshold signal, a level of the sensing threshold signal depending on a threshold voltage of the aging monitoring transistor, a reference threshold storage part receiving the sensing threshold signal generated in response to activation of a reference sensing signal and storing a reference threshold voltage, a level of the reference threshold voltage depending on the level of the sensing threshold signal, and a level comparing part enabled in response to the activation of the aging monitoring signal and generating an aging flag signal, a logic state of the aging flag signal depending on a comparison result between the level of the sensing threshold signal and the level of the reference threshold voltage.

Abstract: Memory controllers, memory devices, memory systems and operation methods are provided. A memory controller is to: find, in input data, a binary code to be replaced corresponding to a preset programming level to be replaced, the input data is to be written into a memory cell; and substitute the binary code to be replaced in the input data with a replacement binary code corresponding to a preset replacement programming level, and generate a replacement identifier linking a memory address corresponding to the replacement binary code. The quantity of states is reduced by modifying a data encoding mode of the memory controller to help shorten programming duration of the memory device and reduce disturbance.

Abstract: Apparatuses and methods including multiple read modes for reading data from a memory are described. An example apparatus includes a memory including a first read mode and a second read mode. The memory has a read operation for the first read mode including a first pre-access phase, an access phase, and a first post-access phase. The read operation for the second read mode includes a second pre-access phase, the access phase, and a second post-access phase. The read operation for either the first read mode or the second read mode is performed responsive to the memory receiving a read command. The second pre-access phase is different from the first pre-access phase, with the second pre-access phase having a shorter time than the first pre-access phase measured from receipt of the read command.

Abstract: A method for performing an erasing operation on a memory device is provided. The memory device includes a bottom select gate, a plate line above the bottom select gate, a word line above the plate line, a pillar extending through the bottom select gate, the plate line, and the word line, a source line under the pillar, a drain cap above the pillar, and a bit line formed above the drain cap. A first positive voltage bias is applied to the bottom select gate. A second positive voltage bias is applied to the plate line. The first positive voltage bias to the bottom select gate is reduced. A negative voltage bias is applied to the source line.

Abstract: An amplification circuit includes a sense amplification circuit, including a read node SABL, a complementary read node SABLB, a first node PCS, and a second node NCS; an isolation circuit, coupled to the SABL, the SABLB, a hit line BL, and a complementary hit line BLB, configured to: in a sense amplification stage, couple the SABL to the BL and couple the BLB to the SABLB; an offset cancellation circuit, coupled to the BL, the BLB, the SABL, and the SABLB, configured to: in an offset cancellation stage, couple the BL to the SABLB and couple the BLB to the SABL; and a first power supply circuit, coupled to the PCS, and configured to: acquire memory temperature information, and in the offset cancellation stage, adjust, according to the memory temperature information, a magnitude of a power supply voltage provided to the PCS.

Abstract: Spin-orbit-torque (SOT) segments are provided along the sides of free layers in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT segments injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction in order to improve the efficiency of the switching current applied to the magnetoresistive device.