Patents Examined by Huan Hoang
  • Patent number: 11145338
    Abstract: A semiconductor memory device includes a storage, a buffer, and a control logic. The storage stores a first algorithm data. The buffer stores a second algorithm data that is at least partially different from the first algorithm data. The control logic is configured to selectively receive the first algorithm data and the second algorithm data.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventors: Geonu Kim, Yong Soon Park, Won Sun Park
  • Patent number: 11145811
    Abstract: Resistive memory with core and shell oxides and interface dipoles for controlled filament formation is provided. In one aspect, a ReRAM device includes at least one ReRAM cell having a substrate; a bottom electrode disposed on the substrate; spacers formed from a low group electron negativity material disposed on the bottom electrode; a core formed from a high group electron negativity material present between the spacers; and a top electrode over and in contact with the spacers and the core, wherein a combination of the low group electron negativity material for the spacers and the high group electron negativity material for the core generates an interface dipole pointing toward the core. Methods of forming and operating a ReRAM device are also provided.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Jianshi Tang, Praneet Adusumilli, Reinaldo Vega
  • Patent number: 11139016
    Abstract: Methods, systems, and devices for read refresh operations are described. A memory device may include a plurality of sub-blocks of memory cells. Each sub-block may undergo a quantity of access operations (e.g., read operations, write operations). Based on the quantity of access operations performed on any one sub-block over a period of time, a read refresh operation may be performed on the memory cells of the sub-block. A read refresh operation may refresh and/or restore the data stored to the memory cells of the sub-block, and be initiated based on the memory device receiving an operation code (e.g., from a host device).
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Fabio Pellizzer, Karthik Sarpatwari, Innocenzo Tortorelli, Nevil N. Gajera
  • Patent number: 11139033
    Abstract: A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: October 5, 2021
    Assignees: SAMSUNG ELECTRONICS CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Seungwoo Seo, Byeongho Kim, Jaehyun Park, Jungho Ahn, Minbok Wi, Sunjung Lee, Eojin Lee, Wonkyung Jung, Jongwook Chung, Jaewan Choi
  • Patent number: 11139002
    Abstract: Row and/or column electrode lines for a memory device are staggered such that gaps are formed between terminated lines. Vertical interconnection to central points along adjacent lines that are not terminated are made in the gap, and vertical interconnection through can additionally be made through the gap without contacting the lines of that level.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Everardo Torres Flores, Stephen H. S. Tang
  • Patent number: 11139022
    Abstract: An example of an apparatus includes a plurality of memory cells arranged in a plurality of NAND strings that are connected to a source line and a control circuit connected to the source line. The control circuit is configured to provide a first current to the source line to pre-charge the source line to a target voltage for sensing data states of the plurality of memory cells and provide a second current to the source line to return the source line to the target voltage in a recovery period between sensing data states. The control circuit is configured to provide the second current at any one of a plurality of current levels.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: October 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Kou Tei, Ohwon Kwon, Jongyeon Kim, Chia-Kai Chou, Yuedan Li
  • Patent number: 11127469
    Abstract: A non-volatile semiconductor memory device that achieves downsizing as compared to conventional cases is disclosed. A non-volatile semiconductor memory device has a configuration in which a memory cell is disposed between a programming bit line and a reading bit line. The reading bit line provided between adjacent memory cells is shared by the adjacent memory cells. This configuration of the non-volatile semiconductor memory device, in which the reading bit line is shared by the adjacent memory cells, leads to reduction of the number of reading bit lines as compared to that in a conventional configuration, and further leads to reduction of the area of a control circuit and a sense amplifier circuit connected with the reading bit line, thereby achieving downsizing as compared to conventional cases accordingly.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: September 21, 2021
    Assignee: FLOADIA CORPORATION
    Inventors: Shinji Yoshida, Kazumasa Yanagisawa, Shuichi Sato, Yasuhiro Taniguchi
  • Patent number: 11127465
    Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-Sang Lee
  • Patent number: 11119414
    Abstract: A defect prediction method for a device manufacturing process involving production substrates processed by a lithographic apparatus, the method including training a classification model using a training set including measured or determined values of a process parameter associated with the production substrates processed by the device manufacturing process and an indication regarding existence of defects associated with the production substrates processed in the device manufacturing process under the values of the process parameter, and producing an output from the classification model that indicates a prediction of a defect for a substrate.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: September 14, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Scott Anderson Middlebrooks, Willem Maria Julia Marcel Coene, Frank Arnoldus Johannes Maria Driessen, Adrianus Cornelis Matheus Koopman, Markus Gerardus Martinus Maria Van Kraaij
  • Patent number: 11114135
    Abstract: An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses are also provided.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: September 7, 2021
    Assignee: OVONYX MEMORY TECHNOLOGY, LLC
    Inventors: Gerald Barkley, Nicholas Hendrickson
  • Patent number: 11114142
    Abstract: A reference voltage training circuit may include: a normal buffer configured to generate a first received signal by receiving one of differential signals based on the other; a calibration signal generation circuit configured to generate a second received signal by receiving the one of the differential signals according to a reference voltage, and generate reference voltage calibration signals by comparing the phase of the second received signal to the phase of the first received signal; and a reference voltage generation circuit configured to calibrate the level of the reference voltage according to the reference voltage calibration signals.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: September 7, 2021
    Assignee: SK hynix Inc.
    Inventor: Hee Jun Kim
  • Patent number: 11114176
    Abstract: A One Time Programmable (OTP) memory, includes: a first driver coupled to a reference cell by a first bit line; a second driver coupled to an OTP cell by a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 7, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Hochul Lee, Anil Chowdary Kota, Keejong Kim
  • Patent number: 11107526
    Abstract: Technologies relating to controlling forming process in RRAM devices implemented in a cross-bar circuit using one or more feedback circuits are disclosed. An example apparatus includes an RRAM cell configured to form a channel; a MOSFET having a drain terminal, a source terminal, and a gate terminal, wherein the MOSFET is connected to the RRAM cell via the drain terminal; a TIA connected to the MOSFET via the source terminal; a first signal generator connected to the RRAM cell; a second signal generator connected to the MOSFET via the gate terminal; and a comparator having a first input end, a second input end, and an output end, wherein the comparator is connected to the TIA via the first input end, the second input end is connected to a reference voltage source, and the output end is connected to the first signal generator and the second signal generator.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 31, 2021
    Assignee: TetraMem Inc.
    Inventor: Ning Ge
  • Patent number: 11101389
    Abstract: The present disclosure describes aspects of a dual-use semiconductor device for solar power and data storage. In some aspects, a dual-use semiconductor device is selectively configured to generate power by coupling regions having a same type of doping to form a PN junction by which power is generated in response to light. The generated power may be provided to a load coupled to contacts (e.g., front and backside contacts) of the dual-use semiconductor device. The dual-use semiconductor device is also selectively configurable for data storage by decoupling the regions of the same type of doping to provide respective data storage access terminals for accessing (e.g., writing or reading) a bit value that is stored as a level of charge by a floating-gate structure of the dual-use semiconductor device. By so doing, solar power arrays implemented with dual-use semiconductor devices may also provide data storage functionality.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: August 24, 2021
    Assignee: Marvell Asia PTE, Ltd.
    Inventors: Vijay Ahirwar, Sri Varsha Rottela, Nilesh N Khude, B Hari Ram
  • Patent number: 11100963
    Abstract: A data first-in first-out (FIFO) circuit includes a register unit, a plurality of data multiplexers, and an output multiplexer. The register unit includes a plurality of decoders and a plurality of N registers. The decoders are used for outputting a plurality of decoded signals in response to a plurality of corresponding input control signals and at least one input enabling signal. The N registers are configured to receive input data in response to the corresponding decoded signals from the corresponding decoders. The data multiplexers each are coupled to M ones of the registers, wherein N and M are positive integers, N is equal to or greater than four, M is equal to or greater than two, and N is greater than M. The output multiplexer, coupled to the data multiplexers, is used for providing a corresponding output from the data multiplexers sequentially.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: August 24, 2021
    Assignee: ELITE SEMICONDUCTOR MICROELECTRONICS TECHNOLOGY INC.
    Inventors: Po-Hsun Wu, Jen-Shou Hsu
  • Patent number: 11100985
    Abstract: A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: August 24, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Nagashima, Hirofumi Inoue
  • Patent number: 11094370
    Abstract: Disclosed embodiments relate to enhanced auto-precharge memory scheduling. In one example, a system includes a memory having a matrix of storage cells, which, responsive to a row address strobe (RAS) signal, activates a given row, responsive to a column address strobe (CAS) signal, selects storage cells in the given row, and, responsive to a combined auto-precharge (AP) and CAS signal, accesses, then closes the given row. A memory controller selects a memory request from a memory request queue, generates the RAS signal to activate a row, when another memory request to the row is enqueued, generates the CAS signal to select a storage cell, when another memory request to a same bank but a different row is enqueued, generates the combined AP and CAS signal, and, when no memory request to the same bank is enqueued, generates the CAS signal only, allowing a close timer to close the row.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Shadi T. Khasawneh, Mukund Ramakrishna
  • Patent number: 11087819
    Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Timothy B. Cowles, Dean D. Gans, Jiyun Li, Nathaniel J. Meier, Randall J. Rooney
  • Patent number: 11087850
    Abstract: Algorithms for fast data retrieval, low power consumption in a 3D or planar non-volatile array of memory cells, connected between an accessible drain string and a floating, not directly accessible, source string, in a NOR-logic type of architecture, are presented.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: August 10, 2021
    Assignee: SUNRISE MEMORY CORPORATION
    Inventor: Raul Adrian Cernea
  • Patent number: 11074971
    Abstract: Disclosed herein is a memory cell. The memory cell may act both as a combined selector device and memory element. The memory cell may be programmed by applying write pulses having different polarities. Different polarities of the write pulses may program different logic states into the memory cell. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities of the write pulses.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Innocenzo Tortorelli, Stephen Tang, Christina Papagianni