Abstract: Various embodiments include a computing device memory system having a memory device, a memory physical layer communicatively connected to the memory device, a first input/output (IO) voltage supply electrically connected to the memory device and to the memory physical layer, and a second TO voltage supply electrically connected to the memory device and to the memory physical layer, in which the memory device and the physical layer are configured to communicate data of a memory transaction using a 3 level pulse amplitude modulation (PAM) IO scheme.

Abstract: The present disclosure includes apparatuses and methods for acceleration of data queries in memory. A number of embodiments include an array of memory cells, and processing circuitry configured to receive, from a host, a query for particular data stored in the array of memory cells, wherein the particular data corresponds to a search key generated by the host, search portions of the array of memory cells for the particular data corresponding to the search key, determine data stored in the portions of the array of memory cells that matches the search key, and transfer the data that matches the search key to the host.

Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

Abstract: A semiconductor apparatus includes a command decoding circuit and an enable signal generation circuit. The command decoding circuit generates an operation code and a strobe pulse based on a command signal and a clock signal. The enable signal generation circuit generates a seed signal based on the operation code and the strobe pulse and generates an enable signal by shifting the seed signal. The enable signal generation circuit generates a plurality of guard keys based on a plurality of operation codes and the strobe pulse and prevents the generation of the enable signal for a predetermined time when the plurality of guard keys are not sequentially enabled.

Abstract: Memory devices and methods of operating memory devices in which refresh management operations can be scheduled on an as-needed basis for those memory portions where activity (e.g., activations in excess of a predetermined threshold) warrants a refresh management operation are disclosed. In one embodiment, an apparatus comprises a memory including a memory location, and circuitry configured to determine a count corresponding to a number of activations at the memory location, to schedule a refresh management operation for the memory location in response to the count exceeding a first predetermined threshold, and to decrease the count by an amount corresponding to the first predetermined threshold in response to executing the scheduled refresh management operation. The circuitry may be further configured to disallow, in response to determining that the count has reached a maximum permitted value, further activations at the memory location until after the count has been decreased.

Abstract: An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.

Abstract: Apparatuses, systems, and methods for row hammer based cache lockdown. A controller of a memory may include an aggressor detector circuit which determines if addresses are aggressor addresses or not. The controller may include a tracker circuit which may count a number of times an address is identified as an aggressor, and may determine if the aggressor address is a frequent aggressor address based on the count. If the address is a frequent aggressor address, a cache entry associated with the frequent aggressor address may be locked (e.g., for a set amount of time). In some embodiments, the controller may include a second tracker which may determine if the frequent aggressor address is a highly attacked address. An address mapping associated with the highly attacked address may be changed.

Abstract: When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

Abstract: An electronic apparatus includes a circuit board, a memory chip mounted on the circuit board, a memory controller to control an operation of the memory chip, a conductive pattern including a first control line to connect from a first terminal of the memory chip to a first terminal of the memory chip and a second control line to connect from a second terminal of the memory controller to a second terminal of the memory chip, and a capacitive element to provide a termination voltage. The first control line is connected to the capacitive element and the second control line is not connected to the capacitive element.

Abstract: A write line circuit includes a power supply node configured to carry a power supply voltage level, a reference node configured to carry a reference voltage level, an output node, first and second switching devices coupled in series between the output node and the power supply node, and a third switching device directly coupled to each of the output node and the reference node. The first switching device is configured to selectively couple the output node to the second switching device responsive to a first data signal, the second switching device is configured to selectively couple the first switching device to the power supply node responsive to a second data signal, and the third switching device is configured to selectively couple the output node to the reference node responsive to the first data signal.

Abstract: A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

Abstract: A voltage regulator and a semiconductor memory device having the same are disclosed. The voltage regulator includes an amplifier configured to amplify a difference between a reference voltage and a feedback voltage to generate an amplifier output voltage, a voltage feedback unit connected between an output supply voltage generation node and a ground voltage and configured to generate the feedback voltage, a first transfer gate unit connected between an input supply voltage and the voltage generation node and driven in response to the amplifier output voltage to provide first current, a current load replica unit connected between the voltage generation node and the ground voltage and configured to consume the first current, and a transfer unit connected between the input supply voltage and the voltage generation node and driven in response to the amplifier output voltage when the current load unit performs an operation, to provide second current.

Abstract: A memory circuit includes a bank of non-volatile memory (NVM) devices, a plurality of high-voltage (HV) drivers, a global HV power switch configured to generate a HV power signal, and a plurality of HV power switches coupled to the global HV switch. A first HV power switch of the plurality of HV power switches is coupled to each HV driver of the plurality of HV drivers, the first HV power switch of the plurality of HV power switches is configured to output a power signal responsive to the HV power signal, and each HV driver of the plurality of HV drivers is configured to output a HV activation signal to a corresponding column of the bank of NVM devices responsive to the power signal.

Abstract: When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract: A semiconductor memory device according to an embodiment includes a plurality of planes including a plurality of blocks each being a set of memory cells, and a sequencer configured to execute a first operation and a second operation shorter than the first operation. Upon receiving a first command set that instructs execution of the first operation, the sequencer is configured to execute the first operation. Upon receiving a second command set that instructs execution of the second operation while the first operation is being executed, the sequencer is configured to suspend the first operation and execute the second operation or execute the second operation in parallel with the first operation, based on an address of a block that is a target of the first operation and an address of a block that is a target of the second operation.

Abstract: Methods, systems, and devices for memory clock management and estimation procedures are described. A host device may determine a quantity of clock cycles associated with a duration for accessing a memory cell of a memory array based on truncating a value of a first parameter associated with another duration for a clock to perform a clock cycle. The host device may estimate a value of a second parameter related to (e.g., inversely proportional) to the truncated value of the first parameter and related to (e.g., directly proportional) to a correction factor, and may adjust (e.g., truncate) a third parameter to determine the quantity of clock cycles. Additionally or alternatively, the host device may adjust (e.g., perform a ceiling operation on) the second parameter to determine the quantity of clock cycles. The host device may access the memory cell based on the quantity of clock cycles.

Abstract: An embodiment provides a data processing circuit and a device. The circuit includes: a first bank group 201 and a second bank group 202; a write circuit 203; and a read circuit 204. The write circuit 203 includes a write input cache circuit 2031, and is configured to: receive stored data from a write bus 206 through the write input cache circuit 2031, write the stored data into the first bank group 201 through a first read-write bus 207, and write the stored data into the second bank group 202 through a second read-write bus 208. The read circuit 204 includes a read output cache circuit 2041, and is configured to: read the stored data from the first bank group 201 through the first read-write bus 207, and read the stored data from the second bank group 202 through the second read-write bus 208.

Abstract: In a dynamic flash memory cell including: a HfO2 layer and a TiN layer surrounding a lower portion of a Si pillar standing on a P-layer substrate; a HfO2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N+ layers connected to a bottom portion and a top portion of the Si pillar, and an SGT transistor including: a SiO2 layer surrounding a lower portion of a Si pillar standing on the same P-layer substrate; a HfO2 layer surrounding an upper portion of the Si pillar; a TiN layer; and N+ layers sandwiching the HfO2 layer in a perpendicular direction and connected to a top portion and a middle portion of the Si pillar, bottom positions of the Si pillar and the Si pillar are at the same position A.

Abstract: A semiconductor apparatus implementing a high speed data output and compensating a resetting of a latch circuit is provided. A readout method of a NAND type flash memory includes: a pre-charging step performing a pre-charging on a bit line and a NAND string connected to the bit line through a sense node (SNS); a resetting step performing a resetting on the latch circuit after the pre-charging; and a discharging step performing a discharging on the NAND string after the resetting.