Abstract: A gate delay calculation apparatus includes an Rs parameter storage file for prestoring a parameter for expressing a source resistance value of an RC model as a continuous time function, an Rs determination portion for selectively extracting the parameter prestored in the Rs parameter storage file from the amount of input waveform gradient and output load model and a gate delay determination portion for calculating gate delay based on the source resistance value expressed by the parameter extracted by Rs determination portion and the output load model.

Abstract: An integrated sub-network for a vehicle. The sub-network includes one or more devices which are addressable using IP addresses or object terminology. The sub-network may appear as a single IP address to an external network. The devices may include various servers and clients, such as microphones, cameras, GPS receivers, interfaces to on-board diagnostic systems, communication devices, displays, CD players, radios, speakers, security devices and LANs (local are networks,) to name only a few. Devices may easily be connected or disconnected to upgrade or reconfigure the vehicle's systems, and software and services can easily be provided to the various devices through the network. The network can enable the interaction of various network devices to increase the capabilities or utility of devices which may otherwise be limited. The system therefore provides an easy and inexpensive means to improve or otherwise modify the functionality of the vehicle.

Abstract: Solving simultaneous equations of the moment method defining relationships between a mutual impedence between elements of an electronic apparatus, a wave source, and an electric current flowing in each element so as to simulate an electric current, provided with a unit for calculating the mutual impedance at a sampling frequency and calculating approximation coefficients, when expressing the mutual impedance by approximation expressions in terms of exponents and exponent powers, from the calculated values and sampling frequency; a unit for forming the simultaneous differential equations by setting the approximation coefficients and initial value with respect to the simultaneous differential equations derived by performing a Fourier transform on the simultaneous equations of the moment method in which the approximation expressions are substituted; and a unit for calculating the electric current in the time domain flowing through the specified element by solving the simultaneous differential equations formed.

Abstract: A system for enabling an operator to select a signal indicative of an air mode and a ground mode of an airplane is provided. The air mode is a state of the airplane when the airplane is in the air, and the ground mode is a state of the airplane when the airplane is on the ground. The system includes a plurality of sensors that sense parameters indicative of whether the airplane is sensed in the air or sensed on the ground. Sensed mode logic that determines whether the airplane is sensed in the air or sensed on the ground is provided, The sensed mode logic generates a signal indicative of a sensed ground mode when at leant two sensors indicate the airplane is sensed on the ground. The sensed mode logic generates a signal indicative of a sensed air mode when less than two sensors indicate the airplane is sensed on We ground. An operator interface is also provided. A simulated air mode and a simulated ground mode are selectable via the operator interface.

Abstract: The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.

Abstract: An improved interface between a host computer and a tape drive emulation system includes software interfaces for communicating control, configuration, and policy data and a hardware interface for providing redundancy and fan-out between the main controller and host channels.

Abstract: A network address supply system includes terminal equipments, a server, and a switching HUB to which the terminal equipments and the server are connected via communication lines. Each terminal equipment includes an address supply requesting unit. The switching HUB includes interfaces, a first line data storing unit, and a communication line control unit that when one of the interfaces receives an address supply request broadcast packet from one of the terminal equipments, transmits the address supply request broadcast packet to only an interface corresponding to the interface information stored in the first line data storing unit. The server includes a network address storing unit and an address supplying unit that when receiving the address supply request broadcast packet, broadcasts an address broadcast packet containing an unused network address stored in the network address storing unit as a response packet to the address supply request broadcast packet.

Abstract: A process for obtaining accurate DC convergence in a DC phase of a circuit simulation program for models of field effect transistors (FETs) on a silicon-on-insulator (SOI) substrate. The process comprises running iterations of the DC phase of the circuit simulation program such that error criteria are satisfied, wherein the pseudo-time step changes at each iteration until it reaches a value such that a desired current value is achieved. DC convergence is also achieved by reducing the magnitude of the capacitive and/or charge elements connected to the floating body regions of the field effect transistors on the silicon-on-insulator substrate model during the DC phase to achieve a desired current value.

Abstract: Modems are implemented using a language made of instructions or commands which are based on the types of signals needed to be generated or processed by the modem. That is, the commands are individually tailored to specify the signals to be sent or processed. The modems can be implemented on a digital signal processor or on a host. The language permits a terseness of expression resulting in smaller code, makes it easy to express the needed manipulations required for modem functionality and permits faster execution.

Abstract: A function for adaptively generating test vectors to verify the behavior of a digital system. The function utilizes one or more user-defined verification directives for directing the generation of the test vectors to areas of interest within the digital system. An emulator of the digital system provides dynamic feedback of internal state information to the test vector generation function during the verification. The test vector generation function adaptively generates future verification test vectors based on the user-defined verification directives in view of the internal state information feedback received from the emulator.

Abstract: A system for debugging targets using various techniques, some of which are particularly useful in a multithread environment. These techniques include implementing breakpoints using out-of-line instruction emulation so that an instruction replaced with a breakpoint instruction does not need to be returned to its original location for single-step execution, executing a debugger nub for each target as part of the target task but using a nub task thread for the nub execution that is separate from the target task threads, providing immunity from breakpoints for specified threads such as the nub thread via specialized breakpoint handlers used by those threads, and virtualizing the debugger nub such that a shared root nub provides a uniform interface between the debugger and the target while specialized nubs provide differing functionality based on the type of target being debugged.

Abstract: A system and method for modeling the power consumed by a logic cell in a computer controlled power estimation process estimating the power consumed for an integrated circuit represented by logic cells and connections between cells. The present invention models power consumption within a logic cell associated with a particular designated pin (output, internal, or bidirectional) based on which input (or internal or bidirectional) pin transitioned causing the designated pin to transition. This is referred to as path dependent power modeling. A different power consumption value can be provided for each different modeled transition. The logic cells and the power consumption model for them are stored in a logic cell “library” within the computer system. Path dependent power modeling of the present invention allows library designers to specify a different set of power values depending on which pin transition (e.g., input pin) caused the designated pin to transition.

Abstract: A remote terminal emulator (RTE) is provided in which substantially all of the time elapsing during an emulated use of a computer system under test is categorized and reported. The time required by the computer system under test to respond to command signals transmitted by the RTE is recorded as a receive time and is measured from completion of the transmission of the command signals to recognition of a pattern specified by the RTE as signifying completion of the response by the computer system under test. As a result, the receive time recorded reflects the time required by the computer system under test to (a) process and carry out the command transmitted by the RTE and (b) transmit response data back to the RTE.

Abstract: A method is provided of designing embossed ribs in a plate. The method includes the steps of inputting data of a loaded un-embossed plate and computing orthotropic properties of an embossed ribbed plate material for the plate. The method also includes the steps of computing stresses on the plate and computing optimum orientation of embossed ribs at each point in the plate using the computed stresses and orthotropic properties of the plate. The method includes the steps of computing gradient of objective function and constraints and solving local optimization to obtain a new location and spacing of the embossed ribs in the plate. The method further includes the step of outputting orientation, location and spacing of the embossed ribs in the plate.

Abstract: A processor including in-circuit emulation means comprising a plurality of scan chains of serially connected registers coupled to a means for enabling a serial scan procedure to be carried out, a first scan chain including an address register for providing an address on an address bus to memory, and means for incrementing the value in the address register under control of the processor, the scan chains being arranged to control the processor for incrementing the address register, and the scan chains including a data register coupled to the data bus of the memory to read/write data.

Abstract: Disclosed is a method of designing a memory device that has substantially reduced bitline voltage offsets. The method includes providing a memory core having a depth that defines a plurality of words, and a word width that is defined by multiple pairs of a global bitline and a global complementary bitline. The method also includes designing a six transistor core cell having a bitline and a complementary bitline, and designing a flipped six transistor core cell that has a flipped bitline and a flipped complementary bitline. Further, the method includes arranging a six transistor core cell followed by a flipped six transistor core cell along each of the multiple pairs of the global bitline and the global complementary bitline. Preferably, the bitline of the six transistor core cell is coupled with the flipped complementary bitline of the flipped six transistor core cell, and the complementary bitline of the six transistor core cell is coupled to the flipped bitline of the flipped six transistor core cell.

Abstract: A method and system for optimizing the assembly workcell layout in the context of industrial robotic CAD/CAM/CAE software products. The criterion to be minimized is the cycle time for completing a given sequence of operations, which is achieved by determining the relative positions of peripheral machines on the workcell floor. The method is constructive: each machine is placed one at a time in the robot neighborhood, by means of a modified simulated annealing method. This method yields several possible and optimal positions for a machine and several layouts are thus obtained at the end of execution.

Abstract: This invention describes a multithread HDL logic simulator that is unique from the prior arts. Specifically, it can process both VHDL and Verilog languages in a single program, and it uses special concurrent algorithms to accelerate the tool's performance on multiprocessor platforms to achieve linear to super-linear scalability on multiprocessor systems. Furthermore, the invention includes a unique remote logic simulation and job scheduling capabilities.

Abstract: An operating/controlling device for computer game, including a soft outer wrapping layer, an inner wrapping layer and a signal controlling device sealedly enclosed by the inner wrapping layer. The signal controlling device includes at least one depression member adjacent to the inner wall of the inner wrapping layer. When depressed, the depression member activates an internal signal sensing member to count different data produced during operation of the depression member and input the data to computer software for providing different operational references for the execution software. The operating/controlling device serves to provide a real and live controlling touch feeling for an operator.

Abstract: LAN interface logic (33) receives frames from a LAN segment (32), and frame transport logic (40, 54, 56) transfers frames to and from an ATM network. Forwarding logic (36) is used to (i) determine whether a mapping between a destination address (DA) and a virtual connection (VC) in the ATM network exists, (ii) forward frames containing a known DA to the frame transport logic for transfer to the ATM network, (iii) forward frames containing unknown DAs to the frame transport logic for transfer to a broadcast and unknown server (BUS 74) in the ATM network, and (iv) pass unknown DAs to a LAN emulation client (LEC) processor (42, FIG. 5) to resolve the address. The LEC processor creates a LAN emulation address resolution protocol (LE_ARP) request message containing the unknown DA, and the LE_ARP request message is transferred to a LAN emulation server (LES 76). The LES returns an ATM address of a remote LEC via which the destination node can be reached.