Abstract: Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. First a thin layer of titanium or other refractory metal is deposited, extending into a contact hole, then polysilicon is deposited and a preferential etch removes all of the polysilicon except on the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create conductive sidewalls or a plug. Metal contacts then engage the direct-reacted silicide rather than relying upon step coverage.

Abstract: According to this process, P.sup.+ type parallel bars are implanted in a N type silicon substrate. Thereafter an oxidation above the implanted zones is carried out, then a uniform layer of polycrystalline silicon is deposited that contacts the N type silicon substrate by being directly isolated from the P.sup.+ type grid bars.The present invention allows to manufacture particularly miniaturized vertical junction field-effect transistor structures by a simple process.

Abstract: A method of fabricating an integrated circuit chip including insulated gate field effect transistors, and an integrated circuit chip produced thereby. By a series of complementary self-aligned masking operations, the field oxide is produced from an initial oxide layer to define active device regions in which transistors are formed, and field implants are provided only in the field regions under the field oxide. The transistors are then formed so that the level of the top surface of the gate electrodes corresponds to the level of the top surface of the field oxide. An insulation layer is applied to the sidewalls of the gate electrodes and conductive material is deposited in the recess defined by the gate electrodes and the field oxide. The level of the top surface of the conductive material corresponds to the level of the top surface of the gate electrodes and field oxide. An insulation layer is then applied to the chip surface.

Abstract: A process is described for producing isolated semiconductor devices in a common substrate which have self-aligned and pre-located isolation walls, buried layers, and channel-stops. The isolation walls are formed from a stacked arrangement of a dielectric region and a polycrystalline semiconductor region, above a doped channel-stop region which acts as a field guard. A single mask layer determines the location and spacing of the buried portions of the isolation walls, the channel-stops, and the buried layers.

Abstract: A method for fabricating a connection to a deep buried layer of a bipolar transistor based on SOI technology. In such a method, an epitaxial layer is grown on a single crystalline island formed by recrystallizing a polycrystalline layer on an insulating layer. Then the side surface(s) of the epitaxial layer is tentatively exposed and a conduction path along the side surface(s) is formed extending from the upper surface of the epitaxial layer to the single crystalline island thereunder.

Abstract: A method of forming a silicon nitride coating in situ on a silicon surface by ion milling. The ion milling and silicon nitride formation process are uniquely integrated in semiconductor manufacturing methods to provide several benefits, including contact areas being substantially registered with and self-aligned with functional regions.

Abstract: Gate turn-off field controlled thyristors having high forward blocking capabilities and high blocking gains, and planar, junction gate field effect transistors having high source-to-drain breakdown voltage capability with high differential blocking gain, include a gate region having a plurality of vertical-walled grooves. The devices are fabricated by preferentially etching one surface of a semiconductor substrate, selectively refilling the grooves with a vapor phase epitaxial growth, forming a plurality of first electrode regions on the same surface and interdigitated with the gate region, and forming a second electrode region on the opposite surface of the substrate.

Abstract: A method of manufacturing a semiconductor device wherein a pair of grooves having different depths are formed in a surface of a semiconductor substrate, an epitaxial layer of one conductivity type is grown to a depth enough to fill a shallower one of the grooves, and an epitaxial layer of the opposite conductivity type is further grown to a depth enough to fill a deeper one of the grooves, followed by the step of etching the entire surface to expose the surface of said semiconductor substrate and to leave in each groove an epitaxial layer of mutually different conductivity type and having the same depth and width. A semiconductor device as manufactured by the above method.

Abstract: A method of manufacturing a semiconductor device is set forth to provide a high-frequency bipolar transistor with very fine emitter-base geometry. The method comprises the steps of forming a base region, forming an insulating layer on the base region, and implanting emitter zones and base contact zones in windows in the insulating layer. Only emitter windows are first formed, then the emitter zones are implanted and a masking layer is provided on the insulating layer and in the emitter windows so that the base contact windows can be etched through apertures in the masking layer. The base contact zones are then implanted to the base contact windows.

Abstract: A manufacturing method for VLSI MOS field effect transistor circuits having digital and analog functions performed by short channel transistors and analog transistors integrated on one chip. An n-tube manufacture is performed wherein as soft as possible a field progression in front of a drain-side pn-junction of the analog transistor is achieved. This occurs by means of an additional drain implantation (curve II) with drive-in diffusion before the actual source/drain implantation (curve I) of the n-channel transistors. Both the additional implantation as well as the source/drain implantation are carried out with phosphorous ions. The dosage of the additional implantation lies one to two orders of magnitude below the dosage of the actual implantation, and the penetration depth x in the additional drive-in diffusion is about twice as great as the penetration depth x of the actual source/drain regions. The method is applied in the manufacture of VLSI CMOS circuits.

Abstract: A method of manufacturing stable, low resistance contacts in an integrated semiconductor circuit which involves providing highly doped impurity diffused regions in a silicon substrate, forming a silicon dioxide layer over the highly doped diffused regions and the surrounding substrate, forming contact holes of uniform size in the silicon dioxide layer in selected areas of the highly doped diffused regions, applying a layer including a metal silicide into the holes in contact with the underlying highly doped diffused regions, applying an n.sup.+ -doped polysilicon layer into the contact holes and over the silicon dioxide layer with a thickness corresponding to about half the contact hole side length, and then depositing a layer of predominantly aluminum over the n.sup.+ -doped polysilicon layer.

Abstract: A method for fabricating polysilicon of reduced resistance that may be incorporated in silicon integrated chip manufacturing processes which comprises coating a wafer bearing dielectrically isolated islands with an isolating layer, and depositing thereover a layer of polysilicon. On the surface of the polysilicon layer, a masking layer is formed, and coated with a metallic reflective layer. The portion of the reflective layer, and, optionally, the masking layer, overlaying the interisland area is removed, and the wafer is then exposed to a laser beam, transforming the polysilicon layer into the appropriate resistor material. The remaining metallic and/or masking layer may then be removed, the device exposed to a laser beam again, thereby transforming the polysilicon across the entire surface.

Abstract: There is provided a method of producing a semiconductor device comprising a protecting silicone gel layer which covers a semiconductor chip and bonding wires for taking electrodes out of this chip, and a resin layer which has a smaller thermal expansion coefficient than that of this silicone gel layer at least part of which contacts the silicone gel layer. This method comprises the steps of: thermally expanding the silicone gel layer until it reaches the product environmental guarantee temperature which comes before the cure acceleration reaction in the resin layer; and completely curing the resin layer while maintaining the volume of the silicone gel layer at the same time, thereby fixedly adhering it with the other parts.

Abstract: The present invention is a method for producing an optically enhanced thin film photovoltaic device.The method includes the steps of producing an active layer of semiconductor material wherein the surface of at least one side of the active layer is textured such that the surface includes randomly spaced, densely packed microstructures of predetermined dimensions of the order of the wavelength of visible light in the semiconductor material and attaching a reflecting surface directly to one side of the semiconductor material and making an ohmic contact to the material.

Abstract: A method of manufacturing a semiconductor substrate having dielectric regions is disclosed. The method comprises steps of forming an amorphous silicon layer on the surface of a monocrystalline silicon substrate, annealing a selected surface of said amorphous silicon layer to form a crystallized region intended as an active region, subjecting the obtained structure to a thermal oxidation process to form said dielectric isolation regions, and removing an oxide coating formed on the surface of said crystallized region.

Abstract: A method of fabricating MESFET devices having a submicron line gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of angled evaporation at least one gate wall within said resist cavity, the gate wall defining a shaped gate cavity; depositing gate electrode material within the gate cavity, and removing the resist material. In one embodiment of the invention the gate wall is removed from the gate electrode material, leaving a free-standing electrode. In another embodiment, the gate wall is a permanent part of the electrode structure.

Abstract: Process for producing a laser having several wavelengths, wherein:a first double heterostructure is produced by epitaxy with an active layer having a first composition,the first double heterostructure obtained is etched into the substrate, through a mask having openings in the form of strips, which leads to a substrate on which there are strips of the first double heterostructure separated by etched portions,a second double heterostructure with an active layer having a second composition is grown in the etched portions,a groove is formed between the first and second heterostructures down to the contact layer, andthe groove undergoes proton bombardment.The invention also relates to the laser obtained by this process.Application to optical telecommunications.

Abstract: A bipolar or MOS semiconductor device is produced by self-alignment by (a) forming an insulating film on a semiconductor substrate, (b) forming a first conductive film, on the semiconductor substrate and (c) forming a first masking film having a window. The conductive film is then (d) anisotropically etched to form an opening and then, (e) transversely etched to form a protruding portion of the first masking film. A second masking film is (f) forming a second masking film on the insulating film through the window, (g) an uncovered portion of the insulating film under the protruding portion, is etched and (h) a second conductive film connecting the first conductive film and the exposed portion of the semiconductor substrate is formed.

Abstract: Disclosed is a method of making ohmic and/or Schottky barrier contacts to a silicon semiconductor substrate in which before depositing the metal on silicon semiconductor substrates containing integrated circuits which are covered by a mask having contact windows, the metal is initially deposited on freshly cleaned blank silicon semiconductor substrates mounted in the same vacuum chamber. In this manner any traces of oxygen present in the vacuum chamber are chemisorbed by the blank substrate resulting in deposition of a high quality oxide-free metal contacts on the device substrates.

Abstract: A process for preparing an amorphous silicon semiconductor comprising steps of plasma decomposing silicon compounds and carrying out photolysis of the silicon compounds. According to the process, the growth rate of the semiconductor is greatly increased. The obtained amorphous silicon semiconductor has excellent electrical and optical properties and is useful as a photovoltaic element.