Abstract: In the process according to the invention, in addition to the conventional two photoresist processes for opening the contact holes and for manufacturing the interconnecting pattern, two photoresist processes are used with one photoresist mask each for manufacturing the regions of the planar transistor. Without additional photoresist masks, further semiconductor components, such as integrated resistors and/or lateral transistors are capable of being manufactured. The process is characterized by the fact that, the first photoresist mask is used to manufacture a diffusion masking layer which leaves the base area of the planar transistor unmasked. In this area, the dopings of the collector region are introduced into the substrate and the collector region is diffused. Thereafter, at a relatively small dose rate, there is carried out an implantation of dopings of the base region.

Abstract: Disclosed is a manufacturing method of forming silicon gate, self-aligned MOS-type devices having submicron dimensions. After forming the gate from a highly doped polysilicon layer using a mask, the structure is subjected to a low temperature (700-750 degrees C.) thermal oxidation. Due to enhanced oxidation rate of doped silicon surfaces, a very thick oxide layer over the polysilicon gate sidewalls and a relatively thin oxide layer over the source-drain regions of the substrate are formed. The mask over the polysilicon and the oxide layer over the source-drain regions is removed and source-drain implantation is accomplished followed by selective deposition of metal (e.g. tungsten) over the source-drain regions and the polysilicon gate.In an alternative embodiment of this process, after forming the highly doped polysilicon gate using a mask, lightly doped source-drain regions which are self-aligned and in registry with the gate are formed by ion implantation.

Abstract: An amorphous semiconductor solar cell which comprises a glass substrate and a transparent electrode coated on the substrate. The device also comprises an amorphous semiconductor layer on the transparent electrode, and a rear electrode on the amorphous layer, wherein the average grain diameter of the surface of the transparent electrode ranges from 0.1 .mu.m to 2.5 .mu.m.

Abstract: In a method for the manufacture of a field-effect transistor comprising a substrate and an epitaxial layer located thereon, a V-shaped trench extending from the surface of the epitaxial layer through the epitaxial layer into the substrate is made and a zone is created by implantation in an area located in front of the V-shaped trench.

Abstract: A plurality of microwave semiconductor devices is provided by plating a thin conductive layer on a surface of a wafer of semiconductor material, masking selected portions of the thin conductive layer, and plating unmasked portions of the thin conductive layer to form a thicker, apertured support layer with the apertures in the support layer providing a thin contact. After forming the thicker, apertured support layer, substantial portions of the semiconductor material are removed to form the semiconductor devices as a plurality of mesa shaped diodes, with each one of the semiconductor mesa shaped diodes being formed on a corresponding one of the thin contacts, and with the plurality of mesa shaped diodes being mutually supported by the support layer and integrally formed thin contacts. Each contact and the support are selectively etched to pattern portions of the support and thin contacts into a frame.

Abstract: A method for manufacturing MOSFET type semiconductor devices comprises forming a gate insulation layer and a gate electrode on a single crystal semiconductor substrate; introducing impurities in the substrate using the gate electrode as a mask; introducing accelerated ions deeper into the substrate than the impurities and overlapping at least a portion of the region in which the impurities are introduced in order to convert that portion to an amorphous state; diffusing the impurities into the amorphous region using a heating atmosphere, in order to form source and drain regions and, at the same time, converting the amorphous region to a single crystal; and forming source and drain electrodes in contact with the source and drain regions.

Abstract: A gate-source structure and fabrication method for a surface-gate static induction transistor. The method requires only one masking step during fabrication, thereby eliminating or minimizing mask registration problems during fabrication of the devices. The method and the device are characterized by a two-step etching process which forms T-shaped gate windows in layers of poly-crystalline silicon with different doping levels. The source region is formed during an annealing step from the layer with high doping level. During the annealing step, the gate regions are also formed from gate impurities implanted previously in the gate windows. The source structure and the gate structure are separated by a silicon dioxide protective layer.

Abstract: A JFET having the top gate isolated from the bottom gate by an annulus source region and thin channel region and a top gate ohmic contact region isolated from the bottom gate by a deep isolation region. The isolation region and the top gate contact region are exterior the active channel region.

Abstract: A method for making photovoltaic device comprising the steps of moving at least one substrate into a reaction chamber, causing a plasma reaction of raw material gases in said reaction chamber, thereby forming an amorphous silicon layer of a first conductivity type on said substrate, moving said at least one substrate into a next reaction chamber for a next plasma reaction, causing said next plasma reaction of next raw material gases in said reaction chamber, thereby forming a second amorphous silicon layer of a second conductivity type on said layer of the first conductivity type, the improvement being in after finishing said forming of said an amorphous silicon layer of a first conductivity type, changing the gas atmosphere of said reaction chamber into a different atmosphere which is substantially identical and of equal pressure to the next gas atmosphere of said next reaction chamber, and thereafter moving said substrate to said next reaction chamber.

Abstract: A method for screening double heterostructure laser diodes before mounting and packaging is disclosed. At a normal laser diode operating temperature, a range of pulsed current is passed through the laser diode and the lasing threshold current and slope efficiency of the laser diode are monitored. The laser diode is then subjected to a burn-in process in which it is driven at a high junction temperature for an extended time period. Subsequently the lasing threshold current and slope efficiency are again monitored by applying the same range of pulsed current at the normal operating temperature. If either the threshold current or the slope efficiency have changed by more than a predetermined amount, the laser diode is rejected. Otherwise, the laser diode is gauged as likely to have a lifetime greater than a predetermined value at normal operating conditions so warranting further testing prior to installation into a laser package.

Abstract: A process for isolating a semiconductor device formed in a p-type silicon substrate includes implanting a layer of oxygen ions below the device. The substrate is then heated to 430.degree.-470.degree. C. to activate the silicon/oxygen complexes thus formed and compensate or overcompensate the region thus forming an intrinsic or n-type isolating layer. The technique may be employed for the isolation of DMOS structures.

Abstract: A method for manufacturing a semiconductor device, capable of forming, with good controllability, impurity regions of a low impurity concentration, includes the steps of: forming a gate electrode on a surface of a semiconductor substrate through a gate oxide film; forming a first film on the surfaces of the gate electrode and the semiconductor substrate; forming a non-single-crystalline silicon film to cover the entire surface; forming a second film to cover the entire surface; performing anisotropic etching of the second film to form residual second films on the side walls of that step portion non-single-crystalline silicon film which is formed corresponding to a shape of the gate electrode; performing etching of the non-single-crystalline silicon film by using the residual second films as masks to form residual non-single-crystalline silicon films on the side walls of the gate electrode through the first film; ion-implanting an impurity having a conductivity type opposite to that of the semiconductor substr

Abstract: A single polycrystalline silicon configuration for a memory cell in a static MOS RAM and a method of fabricating the same are described. Three conductivity regions are utilized to form each memory cell. A first conductivity region is formed in the substrate to create a buried ground line and sources and drains of transistors. A second conductivity region is formed within an insulation layer and above the first conductivity region to create a word line, gate regions of the transistors, load resistors, and a power supply line. The power supply line is oriented directly above and parallel to the ground line. A third conductivity region is formed on the surface of the insulation layer to create data lines. The number of process steps and the size of the memory cell are reduced by this configuration.

Abstract: A method for producing an NPN semiconductor device which has a titanium-tungsten barrier metal only in the N type contact windows is disclosed. A semiconductor wafer first undergoes the washed emitter process with the result that the N type collector and emitter contact windows are exposed to bare silicon and the P type contact windows are covered by a layer of silicon dioxide. A layer of titanium-tungsten alloy is deposited on the surface of the wafer. The titanium-tungsten layer is etched out of the P type contact regions using standard photolithographic techniques. The underlying layer of silicon dioxide in the P type contact regions is then also etched away. A layer of aluminum is then deposited across the surface of the wafer. The conductor interconnect photolithography is used to etch away all undesired aluminum. The remaining portions of the titanium-tungsten layer, not covered by aluminum signal lines, are then also etched away.

Abstract: An integrated circuit 14 having an active circuit 19 is formed on a circuit wafer 10. A moat 18 in the field oxide 20 surrounds the active circuit 19. Metallic conductor 30 passes from a location on the active circuit 19 over the moat 18 to a contact area 22. The wafer 10 is covered with a photoshaped silicon nitride layer 18, and a support wafer 40 is secured with adhesive 46 to the circuit side of the circuit wafer 10. The circuit wafer 10 is photoshaped to expose the metallic conductor 30 at the contact area 22, and the contact area 22 is prepared with multiple metal layers 62, 66, 70 for connection to external wiring.

Abstract: A bipolar transistor device is disclosed having a structure wherein a layer of insulating material extends over and covers the structure substrate up to the region of the extrinsic base around the emitter. A very small area conductive base contact is provided to the extrinsic base, and a protective wall of insulating material is located on the sidewall of the base contact to isolate it from the emitter contact. This structure is made possible by a fabrication process incorporating a double-self-alignment technique wherein the base is self-aligned to a window in the insulating material and the emitter is self-aligned to the base.

Abstract: A technique for enclosing microelectronic circuit elements in hermetically sealed packages comprising a planar ceramic substrate with a box-like ceramic cover sealed thereto by a fused glass coating. The glass sealant is applied to the substrate in the form of a paste which thereafter is fired at high temperature and cooled to produce a smooth glass coating. With the cover in place on the substrate, the glass coating is remelted by heat developed by infra-red radiation impinging on all sides of the package structure from heaters in an infra-red furnace. A reflective shield on top of the cover reduces the inflow of heat through that surface, and a heat sink beneath the substrate removes heat, thereby to reduce the temperature rise experienced by circuit elements in the package interior.

Abstract: Semiconductor electrode structure with low parasitic capacitance and method for forming low capacitance first and second electrodes in a semiconductor device, such as a static induction transistor, while avoiding the requirement for precision mask alignment and mask to mask registration. During formation of electrode contacts, the first electrodes are protected by silicon nitride and a low resistivity silicon layer is grown over the semiconductor wafer, forming epitaxial regions over the second electrodes of a polycrystalline region over protected portions of the wafer. The silicon layer is selectively etched by a mixture which removes the polycrystalline region but does not appreciably affect the epitaxial regions. Second electrode metallic contacts are made in enlarged regions of the second electrodes where mask alignment is not critical. The reduction in contact window overlap by metallic contacts reduces parasitic capacitance.

Abstract: Photodiodes (10) are fabricated in a single step diffusion process which exploits the characteristic of certain acceptors to form an anomalous diffusion profile (VI) including shallow and deep fronts (VIa and b) joined by an upwardly concave segment (VIc). By performing this type of diffusion into a low-doped n.sup.- -type body (12) with a carrier concentration (VII) below that of the concave segment, a p.sup.+ --p.sup.- junction (15) is formed at the depth of the concave segment and a p.sup.- --n.sup.- junction (17) is formed at a greater depth. The zone (16) between the junctions is at least partially depleted and forms the active region of a p.sup.+ --p.sup.- --n.sup.- photodiode. Specifically described are InP:Cd photodiodes.

Abstract: A solar cell of high transducing efficiency is provided in the form of a multi-cell laminated construction having n-type light receiving layers. A non-doped layer of the cell on the incident light side has an energy-gap higher than that of the lower cells.