Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

Abstract: A BIOS may include a plurality of protocol drivers and a protocol notification manager configured to receive a protocol notification registration from a consumer driver of the plurality of protocol drivers, receive a unique key associated with the consumer driver, receive a pre-authorized list from a producer driver of the plurality of protocol drivers, the pre-authorized list comprising one or more signed consumer identifiers, each of the one or more signed consumer identifiers identifying a respective one of the plurality of protocol drivers authorized to receive a protocol notification from the producer driver, determine if the unique key successfully decrypts a signed consumer identifier associated with the consumer driver, and perform access control of protocol notification from the producer driver to the consumer driver based on whether the unique key successfully decrypts the signed consumer identifier associated with the consumer driver.

Abstract: A memory device executes a method of controlling power of the memory device. The memory device includes a host interface which receives a command from a host and controls an access to the memory device by the host, a register which is accessible by the host and includes a plurality of different regions, a memory access monitor which monitors which region of the plurality of regions the host accesses, and in response thereto generates a monitoring signal, and a power control manager which selects a power-up group of modules of the memory device in accordance with the monitoring signal and which supplies power to the selected power-up group of modules while not supplying power to any modules of the memory device not belonging to the selected power-up group.

Abstract: A computing device may perform a method that includes determining whether internal time reference data is available while booting the computing device. When the internal time reference data is unavailable, the device clock is set to a default time setting. However, when the internal time reference data is available while booting the computing device, the method includes searching the internal time reference data for a most recent time reference, and setting the device clock to a current time setting based on the most recent time reference.

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Abstract: Synthetizing a hardware description language code into a netlist comprising loads and a multi-clock buffer (MBUF). The MBUF receives a global clocking signal and generates a first and a second related clocking signals. The loads are grouped into a first and a second groups receiving the first and the second clocking signals respectively. A first/second clock modifying leaf are placed between a common node and the first/group groups respectively, wherein the common node is positioned closer in proximity to the first/second groups in comparison to a clock source generating the global clocking signal. The first/second clock modifying leaves receive a least divided clocking signal from the MBUF and generate the first/second clocking signals respectively. The least divided clocking signal is routed from the MBUF to the first/second clock modifying leaves. The first/second clocking signals are routed from the first/second clock modifying leaves to the first/second group respectively.

Abstract: Controlling server power usage in a data center is provided. Power usage among a plurality of server racks in active mode processing a set of workloads in the data center is managed. It is detected that a new server rack in standby mode is being added to the plurality of server racks. It is ensured that the new server rack in the standby mode is properly controlled and monitored prior to transitioning the new server rack to the active mode. It is determined whether power safety criteria are met to safely join the new server rack to the plurality of server racks prior to transitioning the new server rack from the standby mode to the active mode. The new server rack is transitioned to the active mode in without exceeding a power budget for the plurality of server racks in response to determining that the power safety criteria are met.

Abstract: A data reading system for predicting the removal of a data reader from a charging base unit based on the approach of a user's hand. The data reading system includes a data reader with a power supply, a base unit configured to receive the data reader and to charge the power supply of the data reader responsive to the data reader being coupled to the base unit, a sensor configured to detect the approach of a user's hand, and a processor in operable communication with the sensor and the data reader or the base unit. The processor is configured to apply an appropriate action, such as adjust an amount of current used to charge the power supply of the data reader in the base unit responsive to the sensor detecting the approach of the user's hand.

Abstract: Embodiments for managing a computing system are provided. A Root-of-Trust (RoT) device within the computing system is caused to boot. The computing system includes at least one peripheral device, and the RoT device is in operable communication with the at least one peripheral device and a management server. The at least one peripheral device is caused to at least partially boot. The RoT device is caused to retrieve a firmware image associated with the at least one peripheral device from the management server. The at least one peripheral device is caused to reboot utilizing the firmware image.

Abstract: A secure boot system, a secure boot method, and a secure boot apparatus, adapted for a boot apparatus to boot a host device, are provided. The boot apparatus includes a storage device and a processor. In the method, the processor reads a boot code and a boot key for booting the host device from the storage device, and executes a cryptographic algorithm on the boot code by using the boot key to obtain a runtime signature. Besides, the processor reads an original signature from a secure area in the storage device and uses the same to verify the runtime signature. If the runtime signature and the original signature are consistent with each other, the processor provides the boot code for the host device to execute a boot operation.

Abstract: An apparatus for adjusting skew of circuit signal and an adjusting method thereof are provided. The adjusting method includes: providing a controller for executing: based on each of a plurality of clock signals, dividing a circuit to generate a plurality of circuit partitions according to a netlist of the circuit; grouping the circuit partitions to respectively generate a plurality of circuit groups; identifying adjacent states of layout areas of the circuit groups; and, adjusting a skew value of each of the circuit groups according to the adjacent states.

Abstract: Technology is described for a system that includes a power source, a first computing device, a second computing device and a host controller. The power source may provide a direct current (DC) voltage. The first computing device may perform a computing function in a computing environment. The second computing devices may be connected in series to the power source via the first computing device. The first computing device may be directly coupled to the power source and may receive the DC voltage from the power source, and the second computing device may receive a remaining amount of the DC voltage. The host controller may manage computing operations of the first computing device and the second computing device to control load impedance between first computing device and the second computing device.

Abstract: An electronic device according to an embodiment includes a display, and a processor including a plurality of cores, wherein the processor is configured to identify a first application satisfying a designated condition related to boosting of the processor among at least one application running on the electronic device, identify a first instruction set architecture (ISA) of the first application, and boost a frequency of a clock signal applied to at least one core among the plurality of cores included in the processor according to the first instruction set architecture.

Abstract: An initial program load of a system component of a computing environment is performed. A determination is made as to whether one or more signatures of one or more signed binary code components relating to the system component are verified. Based on determining that the one or more signatures are verified, additional verification is performed. The additional verification includes obtaining a select binary code component of one or more binary code components relating to the system component and determining whether the select binary code component is a particular signed binary code component. Based on determining that the select binary code component is the particular signed binary code component, a check is performed. The initial program load is continued based on a successful check.

Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.

Abstract: Provided is an information processing apparatus that performs alteration detection processing on every occasion of starting a program, comprising a writing component capable of writing a setting indicating whether or not to perform the alteration detection processing to a first region referable by a first program that firstly performs the alteration detection processing on another program and to a second region not referable by the first program at a point when the first program is started. The first program performs the alteration detection processing in accordance with the setting written in the first region, and a second program capable of referring to the second region performs the alteration detection processing in accordance with the setting written in the second region.

Abstract: Methods, systems, and computer programs encoded on computer storage medium, for identifying storage devices of an IHS, wherein a BIOS of the IHS is associated with a first enumeration order of the storage devices; enumerating the storage devices such that a particular storage device of the storage devices is enumerated as the first enumerated storage device for both the BIOS and an OS of the IHS, including: determining that an OS installation mode is enabled, and in response, i) exposing only the particular storage device, and ii) disabling the remaining storage devices to; determining that a LUN is set by the BIOS as the first enumerated storage device, including setting an unique identifier (UID) for the particular storage device, and in response fetching data associated with the LUN based on the UID; parsing the LUN data; assigning, based on the parsing, the LUN as the first enumerated storage device.

Abstract: One or more ECU's in an automotive vehicle have a contingent boot and an authenticated boot. When each such ECU is initialized, that ECU performs the contingent boot and the authenticated boot in parallel. The authenticated boot authenticates operational firmware for that ECU that is stored in flash memory of that ECU, starting with initial firmware of the operational firmware. Contingent boot firmware is stored in flash memory of the ECU or is stored in essentially non-alterable memory of the ECU. The contingent boot executes the ECU contingent boot firmware for that ECU. The contingent boot firmware has limited functionality and does not have the ability to flash the flash memory. Upon successful authentication of the initial firmware, the ECU executes the initial firmware and terminates the contingent boot.

Abstract: A boot method is provided for an electronic device. The boot method includes acquiring a boot signal; performing a booting process based on the boot signal; and, based on the boot signal, generating a feedback provided to the boot signal to indicate the booting process.

Abstract: A computer system comprising a scheduled computation module, a work memory storage device, and a controller. The scheduled computation module is configured to receive and process data values according to a predetermined access pattern. The work memory storage device includes one or more work memory banks. The controller is configured to, based on scheduling information associated with the predetermined access pattern, (1) provide data values held by the one or more work memory banks to the scheduled computation module, and (2) selectively control a power state of the one or more work memory banks.