Abstract: Embodiments provide a mutable CRTM schema for ensuring the integrity of a client workload on a single system as updates are made to the firmware used to initialize and run that system by booting a computing system in a secure mode; when successfully validating a boot image for the computing system via a secure verification code that is blocked from write access when the system is booted in a unsecure mode, allowing write access to the secure verification code; and continuing to boot the computing system in the secure mode according to the boot image. When booting the system and unseccessfully validating the boot image at the third time, the system boot is failed.

Abstract: A memory system includes: a memory device suitable for storing an encrypted first boot image including first firmware, an encrypted second boot image including second firmware, and a second authentication key for decrypting the encrypted second boot image, and a controller suitable for controlling the memory device and including a boot memory provided with a boot loader and a first authentication key for decrypting the encrypted first boot image, one or more first processing blocks each of which includes a first core, one or more second processing blocks each of which includes a second core, and a buffer memory.

Abstract: A semiconductor device capable of reducing power consumption is provided. A semiconductor device having a processor executing a plurality of tasks while switching the tasks in synchronization with a supplied operational clock signal includes: a processor-use-rate measuring unit configured to measure a use rate of the processor during a first term; and a frequency-dividing-value selecting circuit and a frequency dividing circuit configured to change a frequency of the operational clock signal supplied to the processor during a second term later than the first term on the basis of the use rate measured by the processor-use-rate measuring unit.

Abstract: The power consumption of a circuit block outside a microcomputer and inside the same system is reduced. An electric power control system includes a first power supply circuit, a semiconductor device having a first circuit block operated by electric power supplied from the first power supply circuit, a state holding circuit that holds an operation state in the first circuit block according to the electric power, an electric power control circuit that controls the electric power supplied to the first circuit block according to the operation state, and a first terminal that outputs a first state signal corresponding to the operation state, a second power supply circuit that controls the supply of electric power according to the first state signal, and a second circuit block operated by the electric power supplied from the second power supply circuit.

Abstract: An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.

Abstract: Circuitry comprises control circuitry to control an operating state of a data handling device of a set of two or more redundant data handling devices configured to perform identical data handling functions; the control circuitry being configured to control an operating state of the respective controlled data handling device as a state transition from a current operating state of that data handling device to a target operating state in response to the issue of a respective state change signal; the control circuitry comprising a detector responsive to issue of the state change signal in respect of a first threshold number representing some but not all of the data handling devices, to detect whether the state change signal is issued in respect of a further one or more of the devices so that a second threshold number of data handling devices is reached.

Abstract: In embodiments, an apparatus includes a burst current monitor, to detect a burst of input current drawn by a SSD from a host above a pre-defined burst threshold, and control logic coupled to the burst current monitor. The control logic, in response to the detection by the burst current monitor of the input current above the burst threshold, causes a capacitor of the SSD to supply an assistance current to the SSD, to reduce the input current drawn by the SSD. In embodiments, the capacitor is a hold-up capacitor disposed in a PLI circuit of the SSD, and the apparatus is integrated within a hold-up control logic sub-circuit of the PLI circuit.

Abstract: An information handling system (IHS) includes a power supply unit (PSU) and a power assist unit (PAU). The PSU provides power to a power rail at a first voltage level when he IHS is in a first platform state, and at a second voltage level when the IHS is in a second platform state. The PAU includes a power storage element, a converter coupled to the power storage element and to the power rail, and a controller. The controller determines whether the IHS is operating in the first or second platform state, directs the converter to provide power from the power storage element to the power rail at the first voltage level when the information handling system is in the first platform state, and to direct the converter to provide power from the power storage element to the power rail at the second voltage level when the information handling system is in the second platform state.

Abstract: A positioning method adapted for a signal transmitting device and a server is provided. The positioning method includes: transmitting a reference signal by using the signal transmitting device having a low power mode and a high power mode; receiving the reference signal and determining a position of the signal transmitting device according to the reference signal and a signal strength and distance curve diagram by the server; and configuring the signal transmitting device to switch to one of the low power mode or the high power mode by the server.

Abstract: Computer components, such as processors and storage devices, provide a performance and consumes an electric power within a range of an upper limit performance and an upper limit power consumption of a power state set for the component among a plurality of power states corresponding to a type of the component. A processor unit determines whether a budget power as a power consumption permitted for a target computer is equal to or more than a power consumption of the target computer or not. When the determination result is false, for at least one component of the target computer, the processor unit selects a power state based on at least one of a priority of an operation using the component and a data characteristic corresponding to the component among a plurality of types of power states corresponding to a type of the component as power state of the component.

Abstract: A system with real time clock continuity is disclosed. The system includes a remote access controller configured to interoperate with a main processor and at least one second system component. The main processor is configured to receive a control from the remote access controller and to initiate a reboot after determining that a time and a tick count are stored in a memory device. The second system component is configured to store the time and the tick count in the memory device. A boot loader of the system is configured to use the time and the tick count to maintain a real time clock during the reboot of the main processor.

Abstract: A method for system power management includes steps of detecting power output of plural power-supplying units (PSUs) and power consumption of plural computing node, so as to indirectly obtain real-time auxiliary power consumption of an auxiliary unit and continuously update maximum auxiliary power consumption; when one of the PSUs is malfunctioned, renewing the maximum sum of the power output of the other PSUs, and applying the difference of the renewed maximum sum of the power outputs and the maximum auxiliary power consumption as a first sum of the node power consumptions of the computing nodes; finally, according to the first sum of the node power consumptions, cutting down the power consumption of at least one of the computing nodes to a first node power consumption.

Abstract: A power distribution node and method of initializing the node, includes a node communication input port and a node communication output port, a first power controller having a first switchable element and a first controller module configured to operate the first switchable element, the first controller module having a first communication input port connected with the node communication input port and a first communication output port, and a second power controller having a second switchable element.

Abstract: A power distribution node and method of associating a permanent identity includes a node communication input port and a node communication output port, a first power controller having a first switchable element and a first controller module configured to operate the first switchable element, the first controller module having a first communication input port connected with the node communication input port and a first communication output port, and a second power controller having a second switchable element.

Abstract: A system includes a central processing unit (CPU) and components, a particular one of including logic to participate in a portion of a boot sequence of the system, where the portion of the boot sequence begins prior to activation of the CPU. The particular component is to send one or more signals to interact with another one of the components in the system during the portion of the boot sequence. The particular component includes a timer block to generate a set of timestamps during the portion of the boot sequence, where the set of timestamps indicates an amount of execution time of the particular component. The particular component sends the set of timestamps to the other component in a particular one of the one or more signals, where the set of timestamps are used to determine execution time of system components to complete the boot sequence.

Abstract: An information processing device includes a processor that calculates a first energy consumption of a first computer during a boot latency when the first computer has already booted and is not executing any job. The boot latency is time taken for boot of a second computer scheduled to execute a second job with the first computer after a first job executed by the first computer. The processor calculates a second energy consumption of the second computer during a waiting time when the second computer has already booted and is not executing any job. The waiting time is obtained by subtracting the boot latency from a time difference between a scheduled end time of the first job and a present time. The processor powers on the second computer when power of the second computer is off and when the second energy consumption becomes equal to or less than a threshold value.