Patents Examined by Hyung-Sub Sough
  • Patent number: 6115262
    Abstract: There is disclosed herein a printed circuit board (PCB) having enhanced mounting pads useful for overprinting solder paste and for repair of the solder joints. The PCB comprises: a dielectric substrate 10 having at least one mounting pad 20 thereon, wherein each mounting pad is arranged in matched relation with a respective termination 32 of an electronic component 30. Each mounting pad 20 includes a main body portion 24 and one or more fingerlike extensions 26 extending outward from the main body portion and away from a projected footprint 34 of the electronic component.
    Type: Grant
    Filed: June 8, 1998
    Date of Patent: September 5, 2000
    Assignee: Ford Motor Company
    Inventors: Bjoern Erik Brunner, Vivek Amir Jairazbhoy, Richard Keith McMillan
  • Patent number: 6115263
    Abstract: A conductive panel adapted to align and retain a printed circuit board modular device carrier assembly. The assembly includes a printed circuit board and a plurality of modular electronic device carriers, each sized to slidably receive a modular electronic device such as a Gigabit Interface Converter. The panel includes at least two generally rectangular openings oriented in a row of opening. The openings are sized to permit the modular electronic device to be slidably disposed therethrough. At least one inwardly extending conductive finger is provided integral with the panel and generally orthogonal to the inner panel surface adjacent the bottom edge of the opening and at least one inwardly extending finger is provided integral with the panel generally orthogonal to the inner panel surface adjacent the upper edge of the opening. The upper and lower fingers securely retain the printed circuit board carrier assembly therebetween when the carrier assembly and panel are in assembled relation.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: September 5, 2000
    Assignee: 3Com Corporation
    Inventors: Paul J. Babineau, David E. Maloney
  • Patent number: 6111205
    Abstract: A connector for coupling high frequency signals between devices includes a substrate having an array of vias for coupling a reference voltage to reference voltage traces that extend along the substrate surface between the devices. Signal traces including device pads for coupling signals to and from the devices alternate with the reference voltage traces. The widths of the reference voltage traces are varied to maintain a substantially constant separation between the reference voltage trace and an adjacent signal trace.
    Type: Grant
    Filed: October 28, 1997
    Date of Patent: August 29, 2000
    Assignee: Intel Corporation
    Inventors: Michael Leddige, John Sprietsma
  • Patent number: 6103978
    Abstract: A multilayered printed wiring board (PWB) with improved probing for in-circuit, functional, and prototype testing. The PWB includes a support layer and at least a top layer disposed over the support layer. The top layer has one or more circuits with traces for measuring signals produced by the circuit. A test-layer for routing the signals to the edge of the board is provided between the top layer and the support layer. The test-layer includes long traces extending from a first location substantially beneath the traces to a second location adjacent to the edge of the board. Contacts for measuring the signals produced by the circuit are provided on the top layer adjacent to the edge of the board. A first set of vias may be used to connect the first ends of the long traces to the traces on the top layer and a second set of vias may be used to connect the second ends of the long traces to the contacts.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: August 15, 2000
    Assignee: Lucent Technologies Inc.
    Inventor: Israel Amir
  • Patent number: 6101085
    Abstract: There is provided a (Ba, Sr) TiO.sub.3 film of higher dielectric constant and less leakage current for serving as a dielectric thin film of a capacitor in a semiconductor memory. DPM (dipivaloylmethanato) compounds of Ba, Sr and Ti are dissolved in THF (tetrahydrofuran) to obtain Ba(DPM).sub.2 /THF, Sr(DPM).sub.2 /THF and TiO(DPM).sub.2 /THF solutions which are used as source material solutions. A (Ba, Sr) TiO.sub.3 film is formed by a CVD method while increasing a relative percentage of a Ti source material flow rate to a sum of Ba source material flow rate and Sr source material flow rate. The film formation is carried out in multiple steps, and annealing is applied in each step after deposition of the film.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: August 8, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takaaki Kawahara, Mikio Yamamuka, Tetsuro Makita, Tsuyoshi Horikawa, Akimasa Yuuki, Teruo Shibano
  • Patent number: 6100475
    Abstract: The specification describes techniques for attaching double sided circuit boards having plated through holes to interconnection substrates using solder bump arrays. The through holes are filled with a high melting point solder which allows solder bumps to be located directly on the through hole thus saving board area and reducing the interconnection length.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: August 8, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Yinon Degani, King Lien Tai
  • Patent number: 6096971
    Abstract: Adaptable, line vibration damping/sag adjustment devices are provided with hollow regions that facilitate drilling of larger holes in the devices so that the devices can hold and clamp lines having correspondingly large diameters.
    Type: Grant
    Filed: October 28, 1998
    Date of Patent: August 1, 2000
    Inventor: Norman Douglas Hull
  • Patent number: 6096980
    Abstract: Crosstalk is reduced in a communications wiring system by an arrangement of circuit traces on a circuit board. The circuit board has circuit traces which are arranged for interconnecting terminals in first and second electrical connectors, wherein the terminals in each connector are associated as signal pairs in the communications wiring system. The circuit board also has at least one non-ohmic trace which is not electrically connected to any of the circuit traces on the board, or to ground. The non-ohmic trace is arranged closely adjacent to at least two of the circuit traces interconnecting different signal pairs so as to couple energy therebetween, whereby crosstalk between the at least two circuit traces is reduced.
    Type: Grant
    Filed: May 14, 1998
    Date of Patent: August 1, 2000
    Assignee: The Whitaker Corporation
    Inventor: Julian Jay Ferry
  • Patent number: 6096979
    Abstract: A primarily polycrystalline but partially amorphous electrical insulator can hermetically seal first and second spaced electrical terminals, one made from an anodized aluminum and the second made from a beryllium copper, Kovar, an alloy of iron and cobalt or an alloy of beryllium, copper, nickel and gold. Nickel may be diffused into the beryllium copper and a noble metal may be deposited on the nickel. The insulator provides a flat meniscus to abut a corresponding electrical insulator in a cable. The insulator may provide an electrical impedance of approximately 50 ohms, an electrical resistivity greater than approximately 10.sup.18 ohms and a dielectric constant of approximately 6.3. The insulator operates satisfactorily in a frequency range to approximately 40 gigahertz.
    Type: Grant
    Filed: July 19, 1993
    Date of Patent: August 1, 2000
    Assignee: Kyle Research Laboratories
    Inventor: James C. Kyle
  • Patent number: 6094335
    Abstract: A method for fabricating a vertical parallel plate capacitor is provided. In the method, a sacrificial layer is formed on at least a portion of a surface. A dielectric layer is conformally formed on the sacrificial layer and an exposed portion of the surface. The dielectric layer is etched so as to leave substantially only a fence of dielectric material along a sidewall of the sacrificial layer. The sacrificial layer is removed, and a conductive layer is deposited on the fence and surface. The conductive layer is etched and planarized so as to form a first capacitor plate along one side of the fence, and a second capacitor plate along the other side of the fence, the first and second capacitor plates being substantially parallel to each other, and transverse sections of the capacitor plates including elongated portions substantially normal to the surface.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: July 25, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Kathleen R. Early
  • Patent number: 6091608
    Abstract: A method and apparatus for attaching a set of components to a printed circuit board is presented. A second board includes the set of components to be attached to the printed circuit board. The second board attaches directly to the printed circuit board by attaching to pins of a through hole device, such as an application specific integrated circuit. The through hole device is mounted on one side of the printed circuit board. The through hole device includes pins which protrude to the other side of the printed circuit board. The second board attaches to the protruding pins on the other side of the printed circuit board.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: July 18, 2000
    Assignee: Compaq Computer Corporation
    Inventors: Kurt Michael Thaller, Eugene Smith
  • Patent number: 6087597
    Abstract: An electronic device assembly (and method for forming the same) including a first substrate having a first surface, a second surface, and a first pad on the first surface thereof; a second substrate having a first surface, a second surface, and a second pad on the second surface thereof, the first pad facing the second pad; a rigid spherical core interposed between the first and second pads; and solder connecting the first and second pads. The first substrate has a through-hole which is provided through the first substrate at a position of the first pad, at least a part of the solder is positioned in the through-hole and at least a part of the spherical core is received in the through-hole. The through-hole has an inner wall which is continuously tapered from the first surface of the first substrate to the second surface of the first substrate.
    Type: Grant
    Filed: July 24, 1995
    Date of Patent: July 11, 2000
    Assignee: NEC Corporation
    Inventors: Yuzo Shimada, Yoshimasa Tanaka, Shinichi Hasegawa, Takayuki Suyama
  • Patent number: 6084765
    Abstract: Integrated circuit capacitors utilize improved sidewall spacers to protect diffusion barrier layers from parasitic oxidation and capacitor electrodes from being overetched. These sidewall spacers include a composite of a material such as Al.sub.2 O.sub.3 or Ta.sub.2 O.sub.5 which contacts the diffusion barrier layer and another material such as silicon dioxide, silicon nitride or spin-on-glass. A preferred integrated circuit capacitor includes a semiconductor substrate, a first interlayer insulating layer having a contact hole therein, on the substrate, and a polysilicon conductive plug in the contact hole. A first capacitor electrode is also provided on the first interlayer insulating layer and extends opposite the conductive plug. To inhibit oxidation of the conductive plug and chemical reaction between the conductive plug and the first capacitor electrode, a diffusion barrier layer is provided between the first capacitor electrode and the conductive plug.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: July 4, 2000
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Byoung-Taek Lee
  • Patent number: 6084764
    Abstract: A capacitor assembly which positively disconnects failing capacitors is disclosed. This assembly will disconnect electrical power from a capacitor when internal pressure builds up inside the capacitor as a result of an internal short circuit. One or more capacitors are connected electrically into a circuit. Terminals are fixedly connected at each end of the capacitor. The protruding ends of the terminals slidably couple the capacitor to a source of alternating current (AC) power. The normal failure mode for capacitors is to develop internal short circuits. The failed capacitor then heats up rapidly and generates internal pressure. This pressure deforms the end portion of the capacitor. When the end of the capacitor moves in a longitudinal axis of motion, the slidable connection of the terminal is moved to a non-contacting position and the electrical connection is interrupted.
    Type: Grant
    Filed: December 21, 1998
    Date of Patent: July 4, 2000
    Assignee: Hamilton Sundstrand Corporation
    Inventor: W. Kyle Anderson
  • Patent number: 6084181
    Abstract: A cord has a jacket for containing wires. The jacket has a plurality of circular portions and a plurality of non-circular portions alternating with each other. The circular portions are substantially circular, and the non-circular portions are substantially non-circular, and may be in the shape of a "C" or "U". The "C" or "U" shape maintains the wires in a predetermined order. A method for forming cord includes alternately: (a) extruding a circular portion having a cross section that is substantially circular around a plurality of wires; and (b) extruding a non-circular portion having a cross section that is substantially non-circular around the plurality of wires. The extrusion is continuous, so that the non-circular portion is adjacent to the circular portion. The non-circular portion may be opened so that the conductors are arranged substantially in a line.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: July 4, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Peter Frederick Lilienthal, II, Troy Paul Million
  • Patent number: 6072124
    Abstract: A covered wire waterproof connection structure including wire members which are conductively connected at a connection portion and resin material which covers around the connection portion. At least one of the wire members comprises a covered wire having a conductive wire portion including plural wire cores between which gaps are formed, and a cover portion formed by coating resin around an outer periphery of the conductive wire portion. The resin material is filled into all of the gaps at a portion of the conductive wire portion.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: June 6, 2000
    Assignee: Yazaki Corporation
    Inventors: Sanae Kato, Nobuyuki Asakura, Keiichi Ozaki, Mineo Takahashi
  • Patent number: 6072120
    Abstract: A top phase transmission line and bottom phase transmission line are stretched between support steel towers so that the bottom phase transmission line is positioned below the top phase transmission line. Each of the transmission lines has at least two conductors, which conductors are arranged to be substantially parallel and are separated by a substantially constant distance by interconductor spacers. An intermediate phase transmission line may be arranged between the top phase transmission line and bottom phase transmission line as well. Such transmission lines are multiconductor transmission lines. In these multiconductor transmission lines, the conductor positioned at the left side in the top phase transmission line and the conductor positioned at the right side in the intermediate phase transmission line or bottom phase transmission line directly below it are connected by a first interphase spacer made of an insulator.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: June 6, 2000
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Yutaka Matsuzaki, Jun Katoh, Takeo Munakata
  • Patent number: 6069323
    Abstract: A surface mount pad and a component to be soldered onto the pad includes a main portion and two extension portions coupled to the main portion. The surface mount pad has an indentation which is defined by the extension portions. The portions extend from the main portion on opposing sides of the indentation. The extension portions are positioned to extend from underneath the component lead. The indentation extends underneath the component lead.
    Type: Grant
    Filed: January 21, 1997
    Date of Patent: May 30, 2000
    Assignee: Dell USA, L.P.
    Inventors: Darrell J. Slupek, Becky J. Clowers
  • Patent number: 6063997
    Abstract: In a gas insulated electric apparatus having gas sections filled with insulating gas, a locating device determines a position of a gas section in which an insulation abnormality is detected, on the basis of a detection signal from sensors disposed in each of predetermined gas sections. At the same time a hindering degree diagnosing device diagnoses the degree and the kind of the insulation abnormality, by comparing a detection signal from the sensors with data stored in a data base. A valve control generates a valve control signal, responding to the locating device and the hindering degree diagnosing device, and in response to the valve control signal, a trip circuit generates a valve opening signal to open an electromagnetic valve disposed in a gas section in which an insulation abnormality is detected.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: May 16, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Fumihiro Endo, Tomoaki Utsumi, Toshio Ishikawa, Shuzo Iwaasa, Tokio Yamagiwa
  • Patent number: 6049039
    Abstract: A printed circuit terminal includes a main terminal body and an integrally formed fixing portion that is coaxial with the terminal body for mounting the terminal to a printed circuit base member. A frusto-conical flange is integrally connected between the body and the fixing portion and has a peripheral surface located in radially outward relation to the body and the fixing portion. The flange includes two surface portions. The first surface portion is adapted to contact and extend from the base member for receiving solder deposited in electrical contact with the base member. A second surface portion is axially adjacent to the first portion and exposes a different surface material than the first portion in order to restrain solder adhesion to the second surface portion.
    Type: Grant
    Filed: November 24, 1997
    Date of Patent: April 11, 2000
    Assignee: Star Micronics Co., Ltd.
    Inventor: Isao Fushimi