Patents Examined by Hyung-Sub Sough
  • Patent number: 6046409
    Abstract: A multilayer microelectronic circuit to be directly mounted on a substrate and to be used, for example, as a resonator. The multilayer microelectronic circuit comprises a plurality of dielectric layers and patterned electrodes which are laminated one upon another to form a laminated structure, the dielectric layers and the patterned electrodes forming an electrical circuit. The laminated structure has side surfaces extending along a direction in which the dielectric layers and the patterned electrodes are laminated. An input line is formed at one of the side surfaces and connected with an input section of the electrical circuit. An output line is formed at one of the side surfaces and connected with an output section of the electrical circuit. A grounding line is formed at one of the side surfaces and connected with a grounding section of the electrical circuit. Additionally, a signal line formed at one of the side surfaces, for connecting sections of the electrical circuit.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: April 4, 2000
    Assignee: Ngk Spark Plug Co., Ltd.
    Inventors: Tetsuya Ishii, Hiroshi Katagiri, Tadashi Shingaki, Tatsuya Takemura
  • Patent number: 6037547
    Abstract: A number of non-circular vias are defined in a printed wiring board layer. The vias are preferably elliptical, with their long dimensions oriented at an angle to the primary axes of the via or grid array. By providing elongated, non-circular vias, it is possible to decrease the pitch of the via array, or provide improved routing of escape traces.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: March 14, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard C. Blish, II
  • Patent number: 6015955
    Abstract: A device and method for enabling the reworkability of an integrated circuit. The device includes a wirebond chip having a bottom surface and a carrier substrate having a first surface and a second surface. The first surface and second surface of the carrier substrate are electrically connected through a series of vias. A bonding agent is used to mechanically attach the wirebond chip to the carrier substrate in addition to wirebonds for electrically connecting the wirebond chip to the substrate. The substrate is attached to a multi-chip module (MCM) by ball grid array (BGA) or controlled collapse chip connection (C4) attaching process.
    Type: Grant
    Filed: June 20, 1997
    Date of Patent: January 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: Mukta Shaji Farooq, Raymond Alan Jackson, Sudipta Kumar Ray
  • Patent number: 6011222
    Abstract: A substrate for mounting an electronic part and a method for producing the same, which allows a conductive pin to be inserted and secured in a through hole without exerting any damage thereto. The substrate for mounting an electronic part is formed of a through hole piercing an insulating substrate and a conductive pin with its head inserted into the through hole. The head of the conductive pin is provided with a plurality of projections to its side wall, each projecting radially in 4 or more directions. Those projections form a plurality of pairs, each of which is extending in an opposite direction from an axial center of the head. Those projection pairs include a primary projection pair having a largest length and a secondary projection pair having a second largest length. The length of the primary projection pair is equal to or more than an inside diameter of the through hole.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: January 4, 2000
    Assignee: IBIDEN Co., Ltd.
    Inventors: Masataka Sekiya, Tsunehisa Takahashi, Akihiro Demura, Takuji Asai
  • Patent number: 6005194
    Abstract: An a.c. cable has at least one cable core (15) with two concentric conductor arrangements (8, 9) used as forward and return conductors. At least one of the conductor arrangements (8, 9) contains a plurality of conductor layers (L.sub.j and L.sub.j ') made of stranded normally conducting or superconducting individual conductors (3). The individual conductors preferably feature high-T.sub.c superconducting materials. The wire angles (.alpha..sub.j, .alpha..sub.j ') in the individual conductor layers (L.sub.j and L.sub.j ') should be selected so as to minimize losses. A calculation formula for the wire angles (.alpha..sub.j, .alpha..sub.j ') is given for this purpose.
    Type: Grant
    Filed: March 5, 1998
    Date of Patent: December 21, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventor: Gunter Ries
  • Patent number: 5994648
    Abstract: An electrical circuit assembly which requires no solder processing, including an electronic component having terminations arranged on at least one of its surfaces, and a molded curviplanar substrate having circuit traces thereon and a cavity formed therein, wherein the cavity substantially conforms in shape with the electronic component. Proximate the cavity is a plurality of electrical contacts, arranged in matched relation with the respective terminations of the electronic component, with at least one of the electrical contacts being connected to at least one of the circuit traces on the substrate. The cavity and electrical contacts are dimensioned such that an interference fit is provided between the component's terminations and the electrical contacts, such that the component is held within the cavity when the component is placed therein. The component is disposed in the cavity such that its terminations are in physical and electrical connection with their respective electrical contacts.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: November 30, 1999
    Assignee: Ford Motor Company
    Inventors: Andrew Z. Glovatsky, Michael G. Todd, Cuong Van Pham
  • Patent number: 5990419
    Abstract: A primary conductor having a solid wire or wire strands that are enclosed by an insulating coating which has ribs that extend radially outwardly. The insulating coating provides electrical insulation between neighboring conductors. The ribs define air spaces which are between the ribs and space the insulated primary conductors from each other, thereby reducing the overall dielectric constant of the cable assembly. This in turn reduces the line-to-line capacitance between adjacent conductors, thereby minimizing Near End Cross Talk.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: November 23, 1999
    Assignee: Virginia Patent Development Corporation
    Inventor: Stephen B. Bogese, II
  • Patent number: 5986209
    Abstract: A packaged semiconductor device has bottom surface leads having portions of the package adjacent the lead edges excised. The outer leads may take the form of inverted-J leads, short stub leads, vertically bent leads-in-grooves, or may be entirely eliminated. Lead connections are on the bottom package surface, over the top package surface, and/or on the sides and ends of the package, enabling vertical stacking of the devices and simultaneous/alternative coplanar horizontal connections to other semiconductor devices, circuit boards, etc. A mold assembly with a castellated inner surface forms a package with alternating grooves and columns for holding side and end electrical connection surfaces.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: November 16, 1999
    Assignee: Micron Technology, Inc.
    Inventor: Patrick W. Tandy
  • Patent number: 5986877
    Abstract: A capacitor having a central electrode body having sintered metal anode with an electrode lead, the anode having a sintered product produced from a tantalum powder having deagglomerated particles such that the product of the volume mean diameter in microns multiplied by the specific surface area measured in m.sup.2 /g is a number in the range of below about 25. Capacitors having a central electrode with the anode produced from a sintered product produced from a heat treated and oxidized tantalum powder wherein the oxidized particle size is greater than about 0.7 m.sup.2 /g. Capacitors are defined in terms of anodes produced from powders having specified ratios of Scott Bulk Density to surface area or ratio of die fill rate to surface area.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: November 16, 1999
    Assignee: Cabot Corporation
    Inventors: Viren M. Pathare, Bhamidipaty K. D. P. Rao, James Allen Fife, Hongju Chang, Roger W. Steele, Lee M. Ruch
  • Patent number: 5986217
    Abstract: A printed circuit board for minimizing thermally-induced mechanical damage of solder joints electrically connecting electronic components to the printed circuit board. The printed circuit board includes a first substrate, solder pads, and an expansion layer. The first substrate has two substantially parallel major surfaces, and a first coefficient of thermal expansion (CTE). The solder pads are located on one of the major surfaces of the substrate. The expansion layer has a second CTE, different than the first CTE, and is affixed to a portion of one of the major surfaces. The expansion layer is also arranged to provide a predetermined degree of bending for a given temperature change to a portion of the first substrate proximate to the expansion layer and to two of the solder pads, thus forming a concavity in the portion of the substrate.
    Type: Grant
    Filed: October 22, 1997
    Date of Patent: November 16, 1999
    Assignee: Hewlett-Packard Company
    Inventor: Michael J. Strum
  • Patent number: 5977488
    Abstract: A method of numbering an electronic component to be mounted on a printed circuit board (PCB). According to the method, the PCB is divided into a plurality of sections, X-Y coordinate values are allocated to each of the sections, and the allocated coordinate values are printed in the corresponding section. The electronic component number is determined and printed on the PCB in a format of "type of the component--classification of the component--X-Y coordinate values of the corresponding section--serial number of the component".
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: November 2, 1999
    Assignee: LG Electronics, Inc.
    Inventor: Seung Won Jeon
  • Patent number: 5977479
    Abstract: There is disclosed a structure for coupling between a low temperature circuitry cooled by a cooling system and a room temperature circuitry wherein the structure contains a device for electric connection and a second cooling system specifically for cooling of the electric connection.
    Type: Grant
    Filed: October 24, 1994
    Date of Patent: November 2, 1999
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hitoki Tokuda, Michitomo Iiyama
  • Patent number: 5978205
    Abstract: When step parts are formed such that the surfaces of a capacitor element drop down on both the sides of a part served as a gap and the capacitor element is soaked into a conductive paste, the step parts are designed to interrupt the conductive paste to flow up. And, the conductor film is adhered also on the step parts. Thereby, the edges of the electrodes made of the conductor film are not only opposed each other with the gap interpolated therebetween, but also opposed electrodes are formed on the parts of the step parts. Thereby, a high capacitance can be acquired. Further, a resin is coated on a part where an insulating coating is formed, and the resin flows into recessed parts adjacent to the step parts. Therefore, the outside diameter of the insulating coating does not extremely increase.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: November 2, 1999
    Assignee: Taiyo Yuden Co., Ltd.
    Inventors: Takuji Aoyagi, Tetsuo Tatsuno
  • Patent number: 5973907
    Abstract: Multielement capacitors have at least one metal capacitor and at least one ceramic capacitor with common terminals in a common case. The preferred metal capacitance elements have an effective series capacitance of at least 1 microfarad at frequencies of up to 100 kHz. The individual metallic capacitance elements exhibit an ESR of less than 100 milliohms at 100 kHz and a dissipation factor (DF) of less than about 6% at 120 Hz. The ceramic capacitance elements useful in the invention have an equivalent series capacitance of at least about 0.1 microfarads at frequencies of up to about 100 MHz. The individual ceramic capacitance elements have an ESR of less than 20 milliohms at 1 MHz and a dissipation factor of less than 10% at 1 kHz.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: October 26, 1999
    Assignee: Kemet Electronics Corp.
    Inventor: Erik K. Reed
  • Patent number: 5973263
    Abstract: An encapsulation body for enclosing an electronic element is disclosed and which includes a first layer of a slow curing two-part epoxy which is in a flowable state; a second layer of material positioned outwardly of the first layer and which substantially retains the first layer of material on the electronic element while the first layer of material is in a flowable state; and a dam surrounding the electronic element, the first and second layers of material received within the dam.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: October 26, 1999
    Assignee: Micron Communications, Inc.
    Inventors: Mark E. Tuttle, Joseph P. Mousseau, Clay L. Cirino
  • Patent number: 5959254
    Abstract: An insulator has been invented for use between adjacent portions of wire coils of a helical heater wire, the insulator, in one aspect, having a body member with a front, a rear, a first side, a second side, a top, and a bottom, a first groove formed in the front of the body member and extending from the first side to the second side, the first groove for receiving and holding a first portion of a first wire coil. In certain aspects the insulator also has a second groove formed in the rear of the body member spaced apart from the opposite the first groove, the second groove extending from the first side to the second side, the second groove for receiving and holding a portion of a second wire coil adjacent to and spaced apart from the first wire coil. In one aspect the first and second grooves are at a top of the body member and another pair of such grooves are at the bottom of the body member. A heater element has been invented with such an insulator and a heater has been developed with such a heater element.
    Type: Grant
    Filed: October 16, 1997
    Date of Patent: September 28, 1999
    Inventor: Lendell Martin, Sr.
  • Patent number: 5955704
    Abstract: A computer system includes a multi-layer circuit board having first and second routing layers. A component including pads is mounted on the first layer. Crosstalk protection is provided by a plurality of ground vias and signal vias adjacent to the component and extending between the first and second layers. A first circuit trace extends from a first pad along the first layer and between two adjacent ones of the ground vias. A second circuit trace extends from a second pad along the first layer to a signal via at the first layer and from the signal via along the second layer between the two adjacent ground vias.
    Type: Grant
    Filed: November 21, 1996
    Date of Patent: September 21, 1999
    Assignee: Dell U.S.A., L.P.
    Inventors: Leroy Jones, Robert Petty
  • Patent number: 5953202
    Abstract: Materials from which metal film capacitors with plastic or other dielectric films are formed include a plurality of regions or segments defining plates of a capacitor, the regions electrically interconnected by fuse regions which separate a region containing a short circuit fault from the capacitor. The plurality of regions or segments are circular. The fuse regions may be circular or may alternatively be high resistivity regions filling spaces between the plurality of regions or segments. A capacitor having a higher energy storage density and safer construction is wound from these materials using conventional techniques.
    Type: Grant
    Filed: February 6, 1997
    Date of Patent: September 14, 1999
    Assignee: Advanced Deposition Technologies, Inc.
    Inventors: Glenn J. Walters, Gordon E. Walters
  • Patent number: 5949030
    Abstract: Multiple vias are produced coaxially or in axis parallel alignment in a first or primary through-hole in a printed circuit board, chip carrier or like electrical device by producing a primary metallized through hole or via which is then filled or coated with a dielectric material which is also placed on both surfaces of the device at the ends of the via. The dielectric material inside the via can then be provided with at least one coaxial through-hole or multiple axis parallel through holes which can be metallized to form conductive paths between the surfaces of the device. Portions of the dielectric surface layer can be removed to expose contacts to the inner metallized via. Successive coaxial vias can be made in any number by the method of the invention. In addition electrical signal paths can be isolated within voltage or ground co-axial conductors.
    Type: Grant
    Filed: November 14, 1997
    Date of Patent: September 7, 1999
    Assignee: International Business Machines Corporation
    Inventors: Benjamin V. Fasano, Kevin M. Prettyman
  • Patent number: 5949656
    Abstract: A apparatus and method of interconnecting printed circuit boards in an electronic system inside a card cage. The apparatus includes a companion printed circuit board that connects to the main printed circuit board through a first electrical connector, the companion card providing at least one electrical path to a second connector. This second connector connects to the back plane of the card cage, with the back plane providing at least one electrical connection from the second connector to another electrical connector which connects to another companion card connected to the back plane. This method of interconnection avoids requiring flexible cable interconnections, thereby providing a cleaner layout of the electronic system, allowing easy insertion and removal of the main printed circuit boards as well as the companion cards, and providing excellent noise shielding.
    Type: Grant
    Filed: June 1, 1994
    Date of Patent: September 7, 1999
    Assignee: Davox Corporation
    Inventor: Michael Pinault