Abstract: A semiconductor device may include a substrate including a first logic cell and a second logic cell, which are adjacent to each other in a first direction and shares a cell border, a first metal layer on the substrate, the first metal layer including a power line, which is disposed on the cell border to extend in a second direction crossing the first direction and has a center line parallel to the second direction, and a second metal layer on the first metal layer. The second metal layer may include a first upper interconnection line and a second upper interconnection line, which are provided on each of the first and second logic cells. The first upper interconnection line may extend along a first interconnection track and the first direction. The second upper interconnection line may extend along a second interconnection track and in the first direction.

Abstract: A printed circuit board (PCB) includes an identified temperature profiling location. The identified temperature profiling location may be a connection pad from a grid of connection pads on the PCB. The connection pad may be located near a center of the grid of connection pads. The connection pad may be coupled to a no-connect pin of an electronic component that is surface mounted to the PCB. Traces extend from the connection pad to test pads provided near a perimeter of the grid of connection pads. A temperature measurement device may be coupled to the test pads, which enables the temperature measurement device to capture accurate temperature readings underneath the electronic component during a reflow profiling process.

Abstract: A semiconductor device includes: a first semiconductor chip mounted on a chip mounting portion via a first bonding material; and a second semiconductor chip mounted on the first semiconductor chip. Here, the first semiconductor chip has: a protective film located in an uppermost layer; and a first pad electrode exposed from the protective film at an inside of a first opening portion of the protective film. Also, the second semiconductor chip is mounted on a conductive material, which is arranged on the first pad electrode of the first semiconductor chip, via a second bonding material of an insulative property.

Abstract: Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. A series of stadiums, within the stack structure, includes stadiums of differing numbers of staircase sets, such as a stadium having multiple parallel sets of staircases and an additional stadium having a single set of staircases. Each of the staircases includes steps, at ends of the conductive structures, with a same multi-tier riser height. In methods of fabrication, a same initial stadium opening may be concurrently formed for each of the stadiums—regardless of whether the stadium is to include the single set or the multiple parallel sets of staircases—with the steps of the same multi-tier riser height. Electronic systems are also disclosed.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of memory cell groups and a plurality of sense amplification unit groups, and at least two memory cell groups share a same sense amplification unit group.

Abstract: A semiconductor device may include lower electrodes on a substrate, a first upper support layer pattern on upper sidewalls of the lower electrodes, and a dielectric layer and an upper electrode on surfaces of the lower electrodes and the first upper support layer pattern. The lower electrodes may be in a honeycomb pattern with the lower electrodes are at vertexes and center of a hexagon. The first upper support layer pattern may be a first plate shape including openings exposing some of all the lower electrodes. The lower electrodes may form rows in a first direction, the rows arranged in a second direction perpendicular to the first direction. Each opening may expose portions of upper sidewalls of at least four lower electrodes in two adjacent rows. Each of the openings may have a longitudinal direction in the first direction. In semiconductor devices, defects from bending stresses may be decreased.

Abstract: Proposed is an indirect Time-of-Flight (ToF) structure. In the indirect ToF structure, an electric charge storage portion in which electric charge is temporarily stored is provided between a photoelectric conversion portion and a floating diffusion portion, thereby making it possible to perform Correlated Double Sampling (CDS) and to remove noise during readout after an integration time.

Abstract: Disclosed are three-dimensional (3D) semiconductor memory devices and electronic system including the same. The 3D semiconductor memory device may include a substrate including first and second regions, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and having a stepwise structure on the second region, a mold structure adjacent to the stack structure on the first region and including interlayer dielectric layers and sacrificial layers alternately and repeatedly stacked on the substrate, a first separation structure crossing the stack structure and extending along a first direction from the first region toward the second region, and a second separation structure crossing the mold structure and extending in the first direction on the first region. A level of a top surface of the first separation structure may be higher than a level of a top surface of the second separation structure.

Abstract: A wafer structure and a manufacturing method thereof are provided. The wafer structure includes a substrate structure, a first dielectric layer, multiple test pads, a second dielectric layer, and multiple bond pads. The first dielectric layer is disposed on the substrate structure. The test pads are disposed in and exposed outside the first dielectric layer. Each test pad has a probe mark. The second dielectric layer is disposed on the first dielectric layer. The second dielectric layer has a top surface away from the test pads. Multiple bond pads are disposed in and exposed outside the second dielectric layer. Each bond pad is electrically connected to the corresponding test pad. The bond pads have bonding surfaces away from the test pads. The bonding surfaces are flush with the top surface. In the normal direction of the substrate structure, each bond pad does not overlap the probe mark of the corresponding test pad.

Abstract: A semiconductor device includes a first structure including a peripheral circuit and a second structure on the first structure. The second structure includes: a stack structure including first and second stack structures; separation structures passing through the first stack structure; a memory vertical structure between the separation structures and passing through the first stack structure; and a capacitor including first and second capacitor electrodes passing through the second stack structure and extending parallel to each other. The first stack structure includes spaced apart gate electrodes and interlayer insulating layers alternately stacked therewith. The second stack structure includes spaced apart first insulating layers, and second insulating layers alternately stacked therewith. Each of the first and second capacitor electrodes has a linear shape. The first and second insulating layers include a different material from each other.

Abstract: A semiconductor device is provided, including a first well of a first conductivity type disposed on a substrate, a second well of a second conductivity type, different from the conductivity type, surrounding the first well in a layout view, a third well of the first conductivity type, in which a portion of the second well is interposed between the first well and the third well, a first doped region of the second conductivity type that is in the first well and coupled to an input/output (I/O) pad; and at least one second doped region of the first conductivity type that is in the third well and coupled to a first supply voltage terminal. The first doped region, the at least one second doped region, the first well and the third well discharge a first electrostatic discharge (ESD) current between the I/O pad and the first voltage terminal.

Abstract: A bonded body includes a ceramic substrate, a copper plate, and a bonding layer provided on at least one surface of the ceramic substrate and bonding the ceramic substrate and the copper plate, in which the bonding layer contains Ag, Cu, Ti, and a first element being one or two selected from Sn and In, a Ti alloy of Ti and at least one selected from Ag, Cu, Sn, and In existing at a bonding boundary between the copper plate and the bonding layer, and the Ti alloy existing over not less than 30% per a length of 30 ?m at the bonding boundary.

Abstract: A light emitting display device includes a lower substrate, a thin film transistor on the lower substrate, a passivation layer disposed on the thin film transistor and including hydrogen, an overcoating layer disposed on the passivation layer and planarizing the passivation layer, a light emitting element disposed on the overcoating layer and including an anode, a light emitting layer on the anode, and a cathode on the light emitting layer, a bank disposed on the overcoating layer and defining a light emitting area, an adhesive layer on the light emitting element and the bank, and a hydrogen absorbing layer disposed on the adhesive layer and including a hydrogen absorbing filler, wherein a side end of the bank is disposed more inwardly than side ends of the adhesive layer and the hydrogen absorbing layer, wherein the side ends of the adhesive layer and the hydrogen absorbing layer are disposed more inwardly than a side end of the overcoating layer.

Abstract: The semiconductor device includes an air gap extending through at least two metal layers. A dielectric lining layer is used on sidewalls of the opening to ensure a uniform width and protect certain cap layers during enlargement of the opening used to form the air gap. The air gap includes remnants of the dielectric lining layer on sidewalls of the air gap. The air gap reduces the capacitance between a transistor gate in a device layer and adjacent wires and vias used to contact the source and drain of the transistor, compared to air gaps in just a single metal layer or stacked air gaps in different layers.

Abstract: An encapsulated film and a method for encapsulating luminescent device, and a luminescent device, the encapsulated film includes N laminated units, each of the laminated units is composed of barrier layers and surfactant layers which are arranged to be sequentially laminated, the barrier layers and the surfactant layers alternate so that they are adjacent to each other in the encapsulated film, wherein N is an integer greater than or equal to 1. By using the encapsulated film to encapsulate the luminescent device, erosion of water-oxygen to a functional layer of the luminescent device can be effectively reduced, and a service life of the luminescent device is improved.

Abstract: An array of spin qubits relies on a gradient magnetic field to ensure that the qubits are separated in frequency in order to be individually addressable. Furthermore, a strong magnetic field gradient is required to electrically drive the EDSR of the qubits. Quantum dot devices and related methods and systems that integrate magnetic materials in the gates to provide a gradient magnetic field are disclosed. Magnetic materials in different gates may be of different heights to improve frequency separation of neighboring qubits. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein may enable improved control over magnetic fields and their gradients to realize better frequency targeting of individual qubits, help minimize adverse effects of charge noise on qubit decoherence and provide good scalability in the number of quantum dots included in the device.

Abstract: A magnetic domain wall movement element includes a magnetic recording layer which includes a ferromagnetic material; a non-magnetic layer which is laminated on the magnetic recording layer; and a magnetization reference layer which is laminated on the non-magnetic layer, in which the magnetic recording layer has a first ferromagnetic layer, a spacer layer, and a second ferromagnetic layer in order from the non-magnetic layer, a magnetization of the first ferromagnetic layer and a magnetization of the second ferromagnetic layer are antiferromagnetically coupled, and an electrical resistivity of the first ferromagnetic layer is higher than the electrical resistivity of the second ferromagnetic layer.

Abstract: An array substrate includes a base substrate, a driving circuit layer, and a functional device layer which are sequentially stacked; the driving circuit layer is provided with first driving circuits, and each first driving circuit at least includes a driving transistor; and the driving circuit layer includes a first gate layer, a first gate insulation layer, a semiconductor layer, a second gate insulation layer, a second gate layer, an interlayer dielectric layer, and a source-drain metal layer which are sequentially stacked on one side of the base substrate.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. The semiconductor device structure also includes a first bottom layer formed adjacent to the first nanostructures, and a first dielectric liner layer formed over the first bottom layer and adjacent to the first nanostructures. The semiconductor device structure further includes a first source/drain (S/D) structure formed over the first dielectric liner layer, and the first S/D structure is isolated from the first bottom layer by the first dielectric liner layer.

Abstract: The disclosure relates to a trench capacitor device for a superconducting electronic circuit. The trench capacitor device includes a substrate, a first capacitor electrode, and a second capacitor electrode, each electrode including a superconductor and extending into the substrate. The first electrode is circumferentially enclosed by the second electrode such that an inwardly facing surface of the second electrode faces an outwardly facing surface of the first electrode.