Patents Examined by Ida M. Soward
  • Patent number: 10403669
    Abstract: The present disclosure relates to a semiconductor device, an electronic device, and a manufacturing method that can maintain the mounting reliability of an underfill. A chip is formed by a circuit of an imaging element being produced on a Si substrate that is a first substrate and a second substrate being produced on an adhesive formed on the circuit. In this event, a photosensitive material is formed around the chip after the chip is mounted on a mounting substrate by a solder ball or in the state of the chip, then an underfill is formed, and then only the photosensitive material is dissolved. The present disclosure can be applied to, for example, a CMOS solid-state imaging sensor used for an imaging device such as a camera.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: September 3, 2019
    Assignee: Sony Corporation
    Inventors: Masaya Nagata, Kaori Takimoto
  • Patent number: 10403594
    Abstract: A hybrid bonding layer includes a metal inverse opal (MIO) layer with a plurality of hollow spheres and a predefined porosity, and a ball grid array (BGA) disposed within the MIO layer. The MIO layer and the BGA may be disposed between a pair of bonding layers. The MIO layer and the BGA each have a melting point above a TLP sintering temperature and the pair of bonding layers each have a melting point below the TLP sintering temperature such that the hybrid bonding layer can be transient liquid phase bonded between a substrate and a semiconductor device. The pair of bonding layers may include a first pair of bonding layers with a melting point above the TLP sintering temperature and a second pair of bonding layers with a melting point below the TLP sintering temperature.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: September 3, 2019
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Shailesh N. Joshi, Ercan Mehmet Dede
  • Patent number: 10388758
    Abstract: A method for fabricating a semiconductor structure includes providing a substrate. The method further includes implanting the substrate to form a high-voltage well region having a first conductivity type. The method further includes forming a pair of drain drift regions in the high-voltage well region. The pair of drain drift regions are on the front side of the substrate, and the pair of drain drift regions have a second conductivity type opposite to the first conductivity type. The method further includes forming a gate electrode embedded in the high-voltage well region. The gate electrode is positioned between the pair of drain drift regions and laterally spaced apart from the pair of drain drift regions.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: August 20, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Cherng Liao, Manoj Kumar, Chia-Hao Lee, Chung-Te Chou, Ya-Han Liang
  • Patent number: 10388770
    Abstract: One illustrative IC product disclosed herein includes a transistor device including a gate structure positioned above an active region, first and second conductive source/drain structures positioned adjacent opposite sidewalls of the gate structure and an insulating material positioned laterally between the gate structure and each of the first and second conductive source/drain structures. The product also includes first and second air gaps positioned adjacent opposite sidewalls of the gate structure, a gate contact structure that is positioned entirely above the active region and conductively coupled to the gate structure and a source/drain contact structure that is positioned entirely above the active region and conductively coupled to at least one of the first and second conductive source/drain structures.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: August 20, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chanro Park, Christopher M. Prindle
  • Patent number: 10381538
    Abstract: A light emitting device includes a light emitting element, a light-transmissive member, a light guide member and a light reflective member. The light-transmissive member includes a first region directly above a top surface of the light emitting element, and a second region at a lateral side of the first region. The light guide member covers a lateral surface of the light emitting element and a bottom surface of the second region of the light-transmissive member. The light reflective member covers an outer surface of the light guide member. The light-transmissive member contains a fluorescent substance and a light scattering material that is not a fluorescent substance. A concentration of the fluorescent substance in the light-transmissive member is higher in the first region than in the second region. A concentration of the light scattering material in the light-transmissive member is higher in the second region than in the first region.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: August 13, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Hirosuke Hayashi
  • Patent number: 10381553
    Abstract: A magnetoresistive random-access memory (MRAM) device is disclosed. The device described herein has a thermal stability enhancement layer over the free layer of a magnetic tunnel junction. The thermal stability enhancement layer improves the thermal stability of the free layer, increases the magnetic moment of the free layer, while also not causing the magnetic direction of the free layer to become in plan. The thermal stability enhancement layer can be include a layer of CoFeB ferromagnetic material.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: August 13, 2019
    Assignee: Spin Transfer Technologies, Inc.
    Inventors: Mustafa Pinarbasi, Bartek Kardasz
  • Patent number: 10373958
    Abstract: A semiconductor device includes a semiconductor substrate having a gate trench including an upper trench and a lower trench. The upper trench is wider than the lower trench. A gate is embedded in the gate trench. The gate includes an upper portion and a lower portion. A first gate dielectric layer is between the upper portion and a sidewall of the upper trench. The first gate dielectric layer has a first thickness. A second gate dielectric layer is between the lower portion and a sidewall of the lower trench and between the lower portion and a bottom surface of the lower trench. The second gate dielectric layer has a second thickness that is smaller than the first thickness.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: August 6, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Tsuo-Wen Lu, Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
  • Patent number: 10363608
    Abstract: Provided is copper paste for joining including metal particles, and a dispersion medium. The metal particles include sub-micro copper particles having a volume-average particle size of 0.12 ?m to 0.8 ?m, and micro copper particles having a volume-average particle size of 2 ?m to 50 ?m, a sum of the amount of the sub-micro copper particles contained and the amount of the micro copper particles contained is 80% by mass or greater on the basis of a total mass of the metal particles, and the amount of the sub-micro copper particles contained is 30% by mass to 90% by mass on the basis of a sum of a mass of the sub-micro copper particles and a mass of the micro copper particles.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: July 30, 2019
    Assignee: HITACHI CHEMICAL COMPANY, LTD.
    Inventors: Yuki Kawana, Kazuhiko Kurafuchi, Yoshinori Ejiri, Hideo Nakako, Chie Sugama, Dai Ishikawa
  • Patent number: 10367078
    Abstract: Semiconductor devices, FinFET devices and methods of forming the same are disclosed. One of the semiconductor devices includes a substrate and a gate structure over the substrate. The gate structure includes a high-k layer over the substrate, a shielding layer over the high-k layer, and an N-type work function metal layer over the shielding layer. In some embodiments, the shielding layer has a dielectric constant less than a dielectric constant of the high-k layer.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yuan Chang, Che-Hao Chang, Cheng-Hao Hou, Kuei-Lun Lin, Kun-Yu Lee, Xiong-Fei Yu, Chi-On Chui
  • Patent number: 10361276
    Abstract: A trench N-channel field effect transistor has an active area and an edge area. A first pair of parallel-extending deep trenches extends parallel to a side edge of the die. A second pair of parallel-extending deep trenches extends perpendicularly to the side edge, toward the side edge, so that each trench of the second pair terminates into the inside deep trench of the first pair. An embedded field plate structure is embedded in these trenches. A plurality of floating P type well regions is disposed entirely between the second pair of deep trenches, between the active area and the inside deep trench of the first pair. Using this edge area structure, the breakdown voltage BVDSS of the overall device is increased because the breakdown voltage of the edge area is increased as compared to the same structure without the floating P type well regions.
    Type: Grant
    Filed: March 17, 2018
    Date of Patent: July 23, 2019
    Assignee: Littelfuse, Inc.
    Inventor: Kyoung Wook Seok
  • Patent number: 10355132
    Abstract: An insulated-gate field effect transistor includes a substrate having a drift region and a source region of first conductivity type, and a base region and shielding region of second conductivity type therein. The base region forms a first P-N junction with the source region and the shielding region extends between the drift region and the base region. A transition region of first conductivity type is provided, which is electrically coupled to the drift region. The transition region extends between a first surface of the substrate and the shielding region, and forms a second P-N junction with the base region. An insulated gate electrode is provided on a first surface of the substrate. The insulated gate electrode has an electrically conductive gate therein with a drain-side sidewall extending intermediate the second P-N junction and an end of the shielding region when viewed in transverse cross-section.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: July 16, 2019
    Assignee: North Carolina State University
    Inventor: Bantval Jayant Baliga
  • Patent number: 10355116
    Abstract: A power semiconductor device includes: a semiconductor body coupled to a first load terminal and a second load terminal, and includes: a first doped region of a second conductivity type electrically connected to the first load terminal; a recombination zone arranged at least within the first doped region; an emitter region of the second conductivity type electrically connected to the second load terminal; and a drift region of a first conductivity type arranged between the first doped region and the emitter region. The drift region and the first doped region enable the power semiconductor device to operate in: a conducting state during which a load current between the load terminals is conducted along a forward direction; in a forward blocking state during which a forward voltage applied between the load terminals is blocked; and in a reverse blocking state during which a reverse voltage applied between the terminals is blocked.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: July 16, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Markus Bina, Thomas Basler, Matteo Dainese, Hans-Joachim Schulze
  • Patent number: 10355199
    Abstract: An electronic device may include a semiconductor memory, and the semiconductor memory may include a substrate; an interlayer dielectric layer formed over the substrate and patterned to include a contact hole; a lower contact structure formed over the substrate in the contact hole; and a variable resistance element formed over and electrically coupled to the lower contact structure, wherein the lower contact structure comprises: a spacer formed on sidewalls of the contact hole in the interlayer dielectric layer and including a material having a lower etch rate than that of silicon nitride (SiN); a contact plug filling a portion of the contact hole; and a contact pad formed over the contact plug and filling a remaining portion of the contact hole.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 16, 2019
    Assignee: SK hynix Inc.
    Inventors: Hyung-Suk Lee, Do-Yeon Kim
  • Patent number: 10347574
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Dai-Jang Chen, Hsiang-Tai Lu, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung, Po-Yao Chuang
  • Patent number: 10347713
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having first and second planes; first and second electrodes; a first semiconductor region of a first conductivity type in the semiconductor layer; a second semiconductor region of a second conductivity type between the first semiconductor region and the first plane; and a third semiconductor region of the second conductivity type surrounding the second semiconductor region. The third semiconductor region includes a first region, a second region, and a third region. A first region, a second region, and a third region are closer to the second semiconductor region in this order. An amount of second-conductivity-type impurities in the first region, the second region, and the third region is less than that of the second semiconductor region. An amount of second-conductivity-type impurities in the second region is higher than that in the first region and the third region.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: July 9, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tomohiro Tamaki
  • Patent number: 10347627
    Abstract: Semiconductor devices are provided. A semiconductor device includes a gate structure and an adjacent contact. The semiconductor device includes a connector that is connected to the contact. In some embodiments, the semiconductor device includes a wiring pattern that is connected to the connector. Moreover, in some embodiments, the connector is adjacent a boundary between first and second cells of the semiconductor device.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: July 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Moon Gi Cho, Hyeonuk Kim, Jongchan Shin, Eryung Hwang, Jaeseok Yang, Jinwoo Jeong
  • Patent number: 10340212
    Abstract: A semiconductor substrate includes a dielectric layer, a heat dissipation structure and a first patterned conductive layer. The dielectric layer has a surface. The heat dissipation structure is surrounded by the dielectric layer. The heat dissipation structure defines a space and includes a liquid in the space. The first patterned conductive layer is disposed adjacent to the surface of the dielectric layer and thermally connected with the heat dissipation structure.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 2, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Cheng Lee, Yu-Lin Shih
  • Patent number: 10340210
    Abstract: Described examples include a system in package (SIP) device, including: a first leadframe having a first surface and a second surface opposite the first surface; an integrated circuit die including solder bumps on a first surface and having a second opposite surface, the solder bumps mounted to the second surface of the first leadframe; a second leadframe having a first surface including a die pad portion, and a second opposite surface, the die pad portion attached to the second surface of the integrated circuit die; and an inductor mounted to the first surface of the first leadframe, the inductor having terminals with exterior portions electrically connected and mechanically connected to the first surface of the first leadframe, the inductor terminals spaced from one another by a portion of an inductor body, the portion of the inductor body between the inductor terminals spaced from the first surface of the first leadframe by a gap of at least 100 ?ms.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yien Sien Khoo, Siew Kee Lee
  • Patent number: 10340415
    Abstract: A semiconductor device includes a semiconductor structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer provided between the first conductive semiconductor layer and the second conductive semiconductor layer, and a semiconductor device package including the semiconductor device. The active layer includes a plurality of barrier layers and a plurality of well layers. The second conductive semiconductor layer includes a conductive second semiconductor layer and a conductive first semiconductor layer provided on the conductive second semiconductor layer. The conductive second semiconductor layer has a higher aluminum composition than the well layers, and the conductive first semiconductor layer has a lower aluminum composition than the well layers.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: July 2, 2019
    Assignee: LG Innotek Co., Ltd.
    Inventors: Hyun Jee Oh, Rak Jun Choi, Byeoung Jo Kim
  • Patent number: 10340154
    Abstract: Provided is a bonding joining structure in which a heat generating body and a support including a metal are joined to each other via a joint portion composed of a sintered body of copper powder. The support contains copper or gold, the copper or gold being present in at least an outermost surface of the support. An interdiffusion portion in which copper or gold contained in the support and copper contained in the sintered body is formed so as to straddle a bonding interface between the support and the sintered body. Preferably, a copper crystal structure having the same crystal orientation is formed in the interdiffusion portion so as to straddle the bonding interface.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 2, 2019
    Assignee: MITSUI MINING & SMELTING CO., LTD.
    Inventors: Yoichi Kamikoriyama, Shinichi Yamauchi