Patents Examined by Ida M. Soward
  • Patent number: 10784451
    Abstract: A flexible laminate, in which it is possible to achieve both flexibility and durability, is disclosed. A flexible display using the flexible laminate is also disclosed. The flexible laminate includes one or more units of a laminate structure in which two hard layers interposing one or more intermediate layers therebetween are bonded together as one unit. The intermediate layer has viscoelasticity. When the flexible laminate is bent, a neutral plane is formed in each inner portion of the hard layers that are bonded together to interpose the intermediate layer therebetween.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: September 22, 2020
    Assignee: DOW TORAY CO., LTD.
    Inventors: Takeaki Tsuda, Michitaka Suto, Haruna Mizuno, Haruhiko Furukawa, Maki Itoh
  • Patent number: 10784301
    Abstract: Image sensors are provided. An image sensor includes a substrate including a plurality of pixel areas. The substrate has a first surface and a second surface that is opposite the first surface. The image sensor includes a deep pixel isolation region extending from the second surface of the substrate toward the first surface of the substrate and separating the plurality of pixel areas from each other. The image sensor includes an amorphous region adjacent a sidewall of the deep pixel isolation region. Moreover, the image sensor includes an electron suppression region between the amorphous region and the sidewall of the deep pixel isolation region.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: September 22, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyungi Hong, Kook Tae Kim, Jingyun Kim, Soojin Hong
  • Patent number: 10784465
    Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element includes a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: September 22, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Hiroki Ohara, Makoto Hosoba, Junichiro Sakata, Shunichi Ito
  • Patent number: 10784393
    Abstract: A photodetection element is a photodetection element having an incidence surface for light on a back surface of a semiconductor layer, and includes a periodic nano-concave/convex structure provided on a front surface of the semiconductor layer and having convex portions and concave portions constituting a longitudinal resonator and a transverse resonator for the light incident from the incidence surface, the periodic nano-concave/convex structure converting the light into surface plasmons, and a metal film provided to cover the periodic nano-concave/convex structure, a height and an arrangement pitch of the convex portions in the periodic nano-concave/convex structure are set such that a resonance wavelength of the longitudinal resonator and a resonance wavelength of the transverse resonator match, and a thickness of the metal film is equal to or greater than 20 nm.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: September 22, 2020
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Hiroyasu Fujiwara, Wei Dong, Kazutoshi Nakajima, Shohei Hayashi
  • Patent number: 10777604
    Abstract: A light emitting device including first, second, and third LED sub-units, and electrode pads disposed on the first LED sub-unit, electrically connected to the LED sub-units, and including a common electrode pad electrically connected to each of the LED sub-units, and first, second, and third electrode pads connected to a respective one of the LED sub-units, in which the common electrode pad, the second electrode pad, and the third electrode pad are electrically connected to the second LED sub-unit and the third LED sub-unit through holes that pass through the first LED sub-unit, the first, second, and third LED sub-units are configured to be independently driven, light generated in the first LED sub-unit emitted to the outside through the second and third LED sub-units, and light generated in the second LED sub-unit is emitted to the outside through the third LED sub-unit.
    Type: Grant
    Filed: November 22, 2018
    Date of Patent: September 15, 2020
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Hyeon Chae, Seong Gyu Jang, Ho Joon Lee, Chang Yeon Kim, Chung Hoon Lee
  • Patent number: 10770470
    Abstract: Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Toru Tanzawa, Tamotsu Murakoshi, Deepak Thimmegowda
  • Patent number: 10770673
    Abstract: An organic light emitting device (OLED) is provided that includes a cathode and an anode; a blue emitting layer; and at least two hybrid red/green emitting layers. One of the at least two hybrid red/green emitting layers is a cathode side, red/green emitting layer that is disposed between the cathode and the blue emitting layer. The second of the at least two hybrid red/green emitting layers is an anode side, red/green emitting layer that is disposed between the blue emitting layer and the anode. The OLED emits white light.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 8, 2020
    Assignee: The Regents of the University of Michigan
    Inventors: Stephen R. Forrest, Caleb Coburn, Changyeong Jeong
  • Patent number: 10770441
    Abstract: The embodiment provides a display device including an array substrate, an opposite substrate, a plurality of micro light-emitting diodes and a plurality of bank structures. The opposite substrate is disposed opposite to the array substrate. The micro light-emitting diodes are arranged in an array on the array substrate, wherein the micro light-emitting diodes are electrically connected to the array substrate. The bank structures are located between the array substrate and the opposite substrate, wherein the bank structures form a plurality of accommodating regions, and one of the micro light-emitting diodes is located in one of the accommodating regions. A height of the bank structures is more than or equal to a height of the micro light-emitting diodes.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: September 8, 2020
    Assignee: Innolux Corporation
    Inventors: Shu-Ming Kuo, Chih-Yung Hsieh, Kuan-Feng Lee
  • Patent number: 10768137
    Abstract: A gas detecting sensor including a substrate, a gate electrode provided on the substrate, an insulating layer provided on the gate electrode, a source electrode and a drain electrode, provided on the insulating layer, respectively, an n-type channel provided between the source electrode and the drain electrode, and a quantum dot layer provided on the n-type channel and provided so as to have electronic transition energy capable of resonating with vibration energy of a target gas molecule.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: September 8, 2020
    Assignees: LG Chem, Ltd., Korea University Research and Business Foundation
    Inventors: Kwang Seob Jeong, Hang Beum Shin, Dong Sun Choi, Bit Na Yoon, Ju Yeon Jeong
  • Patent number: 10763639
    Abstract: A device may include a lead-frame including a first electrode and a second electrode, a carrier, a set of optical devices mechanically and electrically connected to the first electrode, and a set of electrical connections that electrically connects the second electrode to the set of optical devices. The lead-frame and the carrier may be mechanically connected to each other via a set of interlocking structures associated with the lead-frame and the carrier. The lead-frame and the set of optical devices may have matching coefficients of thermal expansion. The first electrode and the second electrode may be electrically isolated from each other.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: September 1, 2020
    Assignee: Lumentum Operations LLC
    Inventors: Kong Weng Lee, Vincent V. Wong, Jay A. Skidmore, Prasad Yalamanchili, Gity Samadi, Raman Srinivasan, Yongfeng Guan, Slava Khassine
  • Patent number: 10756276
    Abstract: The present specification relates to an organic photodiode including: a first electrode; a second electrode provided to face the first electrode; and an organic material layer having one or more layers provided between the first electrode and the second electrode, in which one or more layers of the organic material layer include the compound of Formula 1, and an organic image sensor including the same.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: August 25, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Bogyu Lim, Sang Ah Kim, Ji Hoon Kim, Seung Jun Yoo
  • Patent number: 10748763
    Abstract: An n?-type epitaxial layer is grown on a front surface of the silicon carbide substrate by a CVD method in a mixed gas atmosphere containing a source gas, a carrier gas, a doping gas, an additive gas, and a gas containing vanadium. The doping gas is nitrogen gas; and the gas containing vanadium is vanadium tetrachloride gas. In the mixed gas atmosphere, the vanadium bonds with the nitrogen, producing vanadium nitride, whereby the nitrogen concentration in the mixed gas atmosphere substantially decreases. As a result, the nitrogen taken in by the n?-type epitaxial layer decreases and the n?-type epitaxial layer including nitrogen and vanadium as dopants is grown having a low impurity concentration.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Tetsuya Miyazawa
  • Patent number: 10748842
    Abstract: The present disclosure is directed to systems and methods for improving the impedance matching of semiconductor package substrates by incorporating one or more magnetic build-up layers proximate relatively large diameter, relatively high capacitance, conductive pads formed on the lower surface of the semiconductor package substrate. The one or more magnetic layers may be formed using a magnetic build-up material deposited on the lower surface of the semiconductor package substrate. Vias conductively coupling the conductive pads to bump pads on the upper surface of the semiconductor package substrate pass through and are at least partially surrounded by the magnetic build-up material.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Zhiguo Qian, Kaladhar Radhakrishnan, Kemal Aygun
  • Patent number: 10748831
    Abstract: Semiconductor packages and methods of forming the same are provided. One of the semiconductor package includes a first die, a dummy die, a first redistribution layer structure, an insulating layer and an insulating layer. The dummy die is disposed aside the first die. The first redistribution layer structure is electrically connected to the first die and having connectors thereover. The insulating layer is disposed over the first die and the dummy die and opposite to the first redistribution layer structure. The insulating layer penetrates through the insulating layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sen-Kuei Hsu, Ching-Feng Yang, Hsin-Yu Pan, Kai-Chiang Wu, Yi-Che Chiang
  • Patent number: 10748998
    Abstract: A semiconductor device in which a threshold voltage is adjusted by a simplified process and in which current characteristics are improved may include a device isolation layer defining an active region in a substrate, a gate electrode extending in a first direction on the active region, a high-concentration impurity region in the active region on a side of the gate electrode and extending in the first direction, and a low-concentration impurity region at least partly surrounding the high-concentration impurity region. The active region may include a plurality of connecting sections below the gate electrode that protrude from the low-concentration impurity region and extend in a second direction that intersects the first direction. The device isolation layer may include a plurality of separating sections that separate the connecting sections from each other.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: August 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Myoung Soo Kim
  • Patent number: 10727181
    Abstract: A fuse structure includes a fusing line including a first portion, a second portion, and a central portion between the first portion and the second portion; and a dummy fuse neighboring the fusing line, the dummy fuse may include: a first air dummy fuse including a plurality of first air gaps extending in a first direction parallel to the fusing line; and a second air dummy fuse including a second air gap extending in a second direction crossing the fusing line.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 28, 2020
    Assignee: SK hynix Inc.
    Inventors: Jae-Hong Kim, Seo-Woo Nam
  • Patent number: 10719762
    Abstract: Some embodiments provide a three-dimensional (3D) circuit structure that has two or more vertically stacked bonded layers with a machine-trained network on at least one bonded layer. As described above, each bonded layer can be an IC die or an IC wafer in some embodiments with different embodiments encompassing different combinations of wafers and dies for the different bonded layers. The machine-trained network in some embodiments includes several stages of machine-trained processing nodes with routing fabric that supplies the outputs of earlier stage nodes to drive the inputs of later stage nodes. In some embodiments, the machine-trained network is a neural network and the processing nodes are neurons of the neural network. In some embodiments, one or more parameters associated with each processing node (e.g., each neuron) is defined through machine-trained processes that define the values of these parameters in order to allow the machine-trained network (e.g.
    Type: Grant
    Filed: December 31, 2017
    Date of Patent: July 21, 2020
    Assignee: XCELSIS CORPORATION
    Inventors: Steven L. Teig, Kenneth Duong, Javier DeLaCruz
  • Patent number: 10720549
    Abstract: In an embodiment a semiconductor layer sequence includes a pre-barrier layer including AlGaN, a pre-quantum well including InGaN having a first band gap, a multi-quantum well structure including a plurality of alternating main quantum wells of InGaN having a second band gap and main barrier layers of AlGaN or AlInGaN, wherein the second band gap is smaller than the first band gap and the main quantum wells are configured to generate a radiation having a wavelength of maximum intensity between 365 nm and 490 nm inclusive, a post-quantum well with a third band gap which is larger than the second band gap, a post-barrier layer including AlGaN or AlInGaN and an electron-blocking layer including AlGaN.
    Type: Grant
    Filed: September 4, 2017
    Date of Patent: July 21, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Werner Bergbauer, Joachim Hertkorn
  • Patent number: 10720405
    Abstract: A semifinished product includes a base structure, wafer structures, a cover structure and a further cover structure. The base structure has an electrically conductive layer and/or an electrically insulating layer. The wafer structures are on the base structure and have electronic components. The cover structure has at least one further layer and covers the wafer structures and part of the base structure. Separate electronic components are arranged on the cover structure and a further cover structure is provided to cover the separate electronic components and part of the cover structure. A component carrier includes a bare die with pads. The bare die is laminated between a base laminate and a cover laminate and has a lateral semiconductor surface being exposed from the base laminate and the cover laminate. A redistribution layer increases spacing of external electric contacts relative to spacing between pads of the bare die.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: July 21, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Heinz Moitzi, Dietmar Drofenik
  • Patent number: 10720494
    Abstract: Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 21, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Cameron Luce, Pernell Dongmo