Abstract: A superconducting device low in power dissipation and high in operating speed is fabricated by use of a combination of a superconductor material and a semiconductor material. The superconducting device having a low power dissipation and high operating speed characteristic according to the present invention is suitable for configuring a large-scale integrated circuit.

Abstract: Disclosed are a reagent for endotoxin-specific assay which comprises an insoluble carrier having immobilized thereon at least an endotoxin-sensitive factor derived from a limulus amebocyte; a kit for endotoxin-specific assay containing said reagent and a substrate for activated factor C or a substrate for clotting enzyme; a method for assaying endotoxin comprising applying a sample solution to said reagent to cause endotoxin in the sample to react with factor C in said reagent and determining a change of a substrate; and a process for preparing said reagent which comprises physically or chemically immobilizing at least an endotoxin-sensitive factor derived from a limulus amebocyte on an insoluble carrier. Endotoxin in a sample, even turbid or colored, can be specifically assayed with ease and rapidness without the influence of a (1.fwdarw.3)-.beta.-glucan.

Abstract: A semiconductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.

Abstract: Disclosed are substantially pure plasmilar polypeptide and antibodies which bind plasmilar.

Abstract: A method for the detection of the presence or absence of antibodies which bind to antigens of an NMA virus Deficiency is disclosed. This method comprises contacting a solution containing antigens of an NMA virus with a biological sample of a patient and detecting the antibody-antigen complexes. Methods for detection of the presence or absence of antigens or nucleic acid sequences specific to an NMA virus are also disclosed. A substantially purified preparation of an NMA virus and a human cell line chronically infected with an NMA virus are also disclosed.

Abstract: Customizable semiconductor/devices, integrated circuit gate arrays and techniques to produce same are disclosed. The devices comprise integrated circuit blanks having a collection of semiconductor elements and at least one metal layer including fusible links interconnecting said collection of semiconductor elements into an inoperably connected integrated circuit blank. At least one metal layer is first etched thereby to define a pattern of conductors. A passivation layer is provided over at least one metal layer, afterwhich at least one metal layer is etched a second time for selectably removing the fusible links, thereby converting the inoperable integrated circuit blank into a selected operable electronic function.

Abstract: A semiconductor device comprises a capacitor consisting of an Al region formed on a semiconductor substrate, an Al oxide film formed on a surface of said Al region, and electrodes opposed to said Al region with interposition of said Al oxide film.

Abstract: A method of passivating a semiconductor device, comprises depositing a first dielectric passivation layer on the surface of the device, forming at least one planarization layer over the first passivation layer from an inorganic spin-on glass solution containing phosphorus and silicon organometallic molecules that are pre-reacted to form at least one Si.O.P bond between the phosphorus and silicon organometallic molecules, and subsequently depositing a second dielectric passivation layer on said at least one planarization layer(s). This results in improved step coverage of the underlying topography and permits much better protection against moisture related degradation than standard vapor phase deposited passivation layers even when the thickness of such layers is increased.

Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

Abstract: Disclosed is a semiconductor device having an internal circuit protected by an electrostatic protective circuit, the internal circuit and electrostatic protective circuit being formed on the same semiconductor substrate. The internal circuit includes MIS elements and has a double-diffused drain structure, while the protective circuit has a single-diffused drain structure. The internal circuit can be, e.g., a DRAM, and the protective circuit can have diffused resistors and clamping MIS elements. The single-diffused drain structure can be formed in the protective circuit on the semiconductor substrate, while providing double-diffused drain structure in the internal circuit on the same substrate, by: (1) scanning the ion implanting apparatus to avoid ion implantation of the first ions into the region of the protective circuit, and/or (2) forming a photoresist film over the region of the protective circuit to prevent ion implantation of the first ions into the protective circuit region.

Abstract: According to the present invention, planar layers of Nitride (first nitride layer), a-Si (first a-Si layer), Nitride (second Nitride layer) and a-Si (second a-Si layer) are laid down over a first metallization layer. A dielectric layer is then laid down on top of the second a-Si layer. A via is opened in the dielectric layer with an etch gas which attacks a small portion of the second a-Si layer which, in effect, serves as a sacrificial etch-stop layer. A titanium layer is laid down over the via and allowed to thermally react with the remainder of the second a-Si layer to form an electrically conductive titanium silicide region in the area of the via the thickness of the second a-Si layer. The reaction is self-limiting and stops at the second Nitride layer. Subsequently a second metallization layer is disposed over the via.

Abstract: There is disclosed a semiconductor device including a plurality of P well regions (4) and a P well region (41) insulated from each other by a plurality of trench isolating layers (10) formed regularly in predetermined spaced relation with each other and having the same depth. The outermost P well region (41) isolatedly formed externally of an outermost trench isolating layer (10A) is made as deep as the trench isolating layers (10) and, accordingly, is made deeper than the P well regions (4) except the outermost P well region (41). This provides for the alleviation of the electric field concentration generated in the bottom edge of the outermost isolating layer of trench structure, thereby achieving the semiconductor device having an improved device breakdown voltage and a method of fabricating the same.

Abstract: The invention relates to a combination of monolithically integrated semiconductor arrays each having a number of prefabricated standard elements that can be connected together using one or more metalization layers to form different signal processing units. The standard elements prefabricated on the semiconductor array comprise a number of base cells, a number of capacitors, a number of output transistors and a number of photodiodes arranged in rows and columns. The base cells each contain a number of npn and pnp transistors and a number of resistors. The common arrangement of base cells for signal processing and a photodiode array arranged in rows and columns in addition to the capacitors and output transistors permit low cost manufacture at short notice and in small production quantities of a wide variety of different photodetectors with integrated electronic circuits.

Abstract: A method of forming an antifuse in an integrated circuit having an insulating layer on a semiconductor substrate is provided. The method comprises forming a first metal interconnection layer on the insulating layer; forming a first barrier metal layer on the first metal interconnection layer; forming an amorphous silicon layer on the first barrier metal layer; forming another barrier metal layer atop the amorphous silicon layer; and forming a second metal interconnection layer on the second barrier metal layer. In at least one of the barrier metal forming steps, the barrier metal is formed by sputtering a barrier metal target which includes a semiconductor dopant, such as dopant.

Abstract: A static-charge protection device for an antifuse includes an additional second-sized aperture smaller in area than the antifuse apertures disposed in the same inter-electrode dielectric layer. Antifuse material is disposed in the second-sized aperture, and the upper electrode extends over the second aperture as well as the first aperture. A preferred process for fabricating the protection device utilizes the step of forming the smaller apertures and forming their antifuse material layers simultaneously with forming the antifuse apertures. A static-charge protection device for an antifuse device includes an additional second-sized aperture larger in area than the first-sized antifuse apertures. Metal plug material is deposited and etched back. A layer of amorphous silicon antifuse material is formed and defined over the first and second sized apertures, the portion formed over the larger partially filled antifuse protection device cell being thinner.

Abstract: A shallow trench isolation structure is formed by a process having a reduced number of steps and thermal budget by filling trenches by liquid phase deposition of an insulating semiconductor oxide and heat treating the deposit to form a layer of high quality thermal oxide at an interface between the deposited oxide and the body of semiconductor material (e.g. substrate) into which the trench extends. This process yields an isolation structure with reduced stress and reduced tendency to develop charge leakage. The structure can be readily and easily planarized, particularly if a polish-stop layer is applied over the body of semiconductor material and voids and contamination of the deposited oxide are substantially eliminated by self-aligned deposition above the trench in the volume of apertures on a resist used to form the trench.

Abstract: A method is provided for forming an improved poly-buffered LOCOS process by forming a pad oxide layer over a substrate. A first nitride layer is formed over the pad oxide layer and a polysilicon layer is formed over the first nitride layer. A second nitride layer is formed over the polysilicon layer. An opening is etched through the second nitride layer, the polysilicon layer, the first nitride layer and the pad oxide layer to expose a portion of the underlying substrate. A field oxide region is then formed in the opening.

Abstract: CMOS integrated circuit buffers typically use a dual-diode electrostatic discharge (ESD) protection technique. However, in some cases that technique inadvertently causes one of the diodes to conduct when a desired signal voltage is present on the bondpad, thereby clipping the desired signal. This occurs, for example, when an output buffer on an unpowered device is connected to an active bus, or when the input buffer of a 3 volt device receives a 5 volt signal. The present invention solves this problem by using a bipolar (e.g., pnp) protection transistor connected between the bondpad and a power supply bus (e.g., V.sub.SS). The base of the transistor is connected to the bondpad through a resistor that provides a time delay due to the R-C time constant that includes distributed capacitance. The time delay allows for a high conduction period, during which an ESD event is conducted through the bipolar transistor, thereby protecting the input or output buffer.

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract: An LC element, semiconductor device and a manufacturing method thereof whereby a channel 22 is formed by applying a voltage to a gate electrode 10 having a predetermined shape formed on a p-Si substrate 30 via an insulation layer 26, whereby a connection is formed between a first diffusion region 12 and a second diffusion region 14 formed at separated positions near the surface of the p-Si substrate 30; both the channel 22 and gate electrode 10 function as inductors, and between these a distributed constant type capacitor is formed, and possessing excellent attenuation characteristics over a wide band. This LC element and semiconductor device can be easily manufactured by using MOS manufacturing technology; in the case of manufacturing as a portion of a semiconductor substrate, component assembly work in subsequent processing can be omitted. Also these can be formed as a portion of an IC or LSI device.