Abstract: A low noise fluoroscopic radiation imager includes a large area photosensor array having a plurality of photosensors arranged in a pattern so as to have a predetermined pitch, and a low noise addressable thin film transistor (TFT) array electrically coupled to the photosensors. The TFT array includes a plurality of low charge retention TFTs, each of which have a switched silicon region that has an area in microns not greater than the value of the pitch of the imager array expressed in microns. The portion of the switched silicon region underlying the source and drain electrodes of the TFT is not greater than about 150% of the portion of the switched silicon region in the channel area of the TFT. The ratio of the TFT channel width to channel length (the distance between the source and drain electrodes across the channel) is less than 20:1, and commonly less than 10:1, with the channel length in the range of between about 1 .mu.m and 4 .mu.m.

Abstract: Disclosed is a semiconductor device comprising a silicon substrate, a pad provided on the substrate and an integrated circuit portion provided in the substrate. The pad and the integrated circuit portion are electrically connected together by a first wiring layer. The pad and the substrate are electrically connected together by a second wiring layer. The second wiring layer includes a fuse portion. The first wiring layer is always grounded via the fuse portion while processing the device.

Abstract: An electrically programmable fuse buried under quartz and layers of polyimide with a specific structure to enhance its "thermal" capabilities. The fuse is designed to "blow" and cool off quickly so as not to cause damage to areas above and surrounding the fuse. A passivation layer is added above the fuse to act as a heat sink and absorb and redistribute the heat generated from one localized area to a broader and cooler area. The materials used for the fuse and the heat sink are selected to be compatible with both oxide and polyimide personalization schemes. Modeling of the fuse enables optimizing the characteristics of the fuse, particularly to transmit to the surface of the passivation layer the thermal wave created during programming of the fuse.

Abstract: A silicon on insulator substrate 8 provides islands of silicon 18 of uniform thickness by using a trench etch process and a silicon nitride layer 20 to provide a thickness control and polish stop for the silicon islands 18.

Abstract: A breakable fuse element is incorporated in a semiconductor integrated circuit device, and is overlain by a multi-level insulating film structure having the lowest insulating film covering the breakable fuse element and a multi-level insulating sub-structure over the lowest insulating film, wherein an etching stopper is inserted between the lowest insulating film and the multi-level insulating film sub-structure so that an etching for a laser hole is exactly terminated at the etching stopper, thereby exactly controlling the remaining thickness over the breakable fuse element.

Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.

Abstract: A novel antifuse structure includes a novel antifuse material layer comprises a first dielectric layer, a first polysilicon layer (which may optionally be lightly doped) disposed over the first dielectric layer, and a second dielectric layer disposed over the first polysilicon layer. The dielectric layers may be formed of silicon nitride, silicon dioxide, silicon oxynitride and combinations of the foregoing. Additional layers may also be included to form D/P/D/P/D, D/P/D/a-Si/D sandwiches, and the like. The polysilicon layer provides the ability to control the breakdown voltage of the antifuse through control of the doping level while maintaining a relatively large thickness of the antifuse material layer resulting in low capacitance for the antifuse. The antifuse material layer is compatible with high temperature processes (500.degree. C.-950.degree. C.) and may be carried out in the range of 400.degree. C.-950.degree. C. making it compatible with a wide range of processes.

Abstract: A bipolar transistor and a bipolar diode are provided at an input pad on an integrated circuit, in order to shunt potential surges caused by electrostatic discharge (ESD). The approach makes use of a bipolar and a diode clamp with an optimized reverse biased breakdown from collector to base to shunt excess current away from sensitive regions with even current distribution for minimal damage. In order to improve the ESD immunity of the positive going ESD with respect to V.sub.SS, the reverse bias breakdowns of the diode and of the transistor's functioning as a collector/base diode are reduced. This circuit provides a simple low cost approach for improving ESD protection, in a process which fits into most standard Cmos process flows with few or no added process steps.

Abstract: In the known method, a plate of a heat-conducting material, for example silicon, is subdivided by means of grooves into blocks which remain connected to one another along break-off edges. The plate is metallized on two sides and (locally) provided with layer-shaped regions comprising solder at the upper side, the diode laser being fastened within each region, after which the blocks are separated from one another by breaking-off. A disadvantage of this method is that the blocks thus obtained are not suitable for a final mounting in which the radiation beam of the diode laser is perpendicular to the carrier plate on which the support body is fastened.

Abstract: The present invention is directed to providing an electrostatic discharge ("ESD") protection cell for use in an integrated circuit device including antifuses. The ESD protection cell is formed simultaneously with the antifuses that it protects and provides protection from ESD during the fabrication of the antifuses. The concept is to use thin undoped or doped polysilicon on top of antifuse material as a block etching mask for the formation of the ESD protection cells by using common etching techniques. This polysilicon mask is placed where the antifuses will be and not where the ESD protection cells will be. The polysilicon mask is then merged with a top polysilicon electrode during later processing. During the block etching process, the antifuse material layer is compromised in the region about the ESD protection cells.

Abstract: A controlled release oral formulation, for human vaccines, are formed in microspherical form. The vaccine is suspended in a polymer matrix. The polymer matrix is formed from at least two highly water soluble biodegradable polymers, selected for example from starch, crosslinked starch, ficoll, polysucrose, polyvinyl alcohol, gelatine, hydroxymethyl cellulose, hydroxyethyl cellulose, hydroxypropyl cellulose, hydroxypropyl-ethyl cellulose, hydroxypropyl-methyl cellulose, sodium carboxymethyl cellulose, cellulose acetate, sodium alginate, polymaleic anhydride esters, polyortho esters, polyethyteneimine, polyethylene glycol, methoxypolyethylene glycol, ethoxypolyethylene glycol, polyethylene oxide,poly(1,3 bis(p-carboxyphenoxy) propane-co-sebacic anhydride, N,N-diethylaminoacetate, block copolymers of polyoxyethylene and polyoxypropylene. The microspheres are coated with a (d,1 lactide-glycolide) copolymer. The coating makes the microspheres more resistant to enzymatic degradation.

Abstract: A multilevel antifuse structure characterized by a substrate, a first antifuse structure formed above the substrate, and a second antifuse structure formed above the first antifuse structure. The first antifuse structure preferably includes a first conductive layer, a first antifuse layer disposed over the first conductive layer, a first dielectric layer disposed over the first antifuse layer and provided with a first via hole, and a first conductive via formed within the first via hole. The second antifuse structure preferably includes a second conductive layer, a second antifuse layer disposed over the second conductive layer, a second dielectric layer disposed over the second antifuse layer and provided with a second via hole, and a second conductive via formed within the second via hole. Preferably, the first antifuse layer and the second antifuse layer are patterned into a plurality of antifuse regions which are either vertically aligned or vertically staggered with respect to each other.

Abstract: An integrated circuit device includes a barrier layer as an underlying layer for a wiring conductor layer. The barrier layer is formed of titanium oxide-titanium nitride or titanium nitride or composite layers of titanium, 2-titanium nitride and titanium nitride. The barrier layer may contain oxygen or carbon. A method of manufacturing an integrated circuit device includes steps of introducing a gas to the vicinity of a substrate disposed within a vacuum chamber, and forming a titanium oxide-titanium nitride thin film or titanium nitride film or the composite film by depositing titanium in vapor phase by using a cluster-type ion source while irradiating the substrate with nitrogen ions. A thin film forming apparatus comprises a cluster type ion source and a gas ion source.

Abstract: Antifuses and gate arrays with antifuses are disclosed that have high thermal stability, reduced size, reduced leakage current, reduced capacitance in the unprogrammed state, improved manufacturing yield, and more controllable electrical characteristics. Some antifuses include spacers in the antifuse via. In some antifuses, the programmable material is planar, and the top or the bottom electrode is formed in the antifuse via. In some gate arrays, the antifuses are formed above the dielectric separating two levels of routing channels rather than below that dielectric.

Abstract: A multilevel metallization is deposited on a microelectronic device base structure (40). The process includes depositing a glassy dielectric layer (48) of a thickness that is from about two to about three times as thick as the topography thickness (D) of the base structure (40). The glassy dielectric layer (48) is heated to a temperature above its glass transition temperature to flow the glassy dielectric layer (48). The glassy dielectric layer (48) is thinned to a preselected thickness, and a first patterned metallization layer (54) is deposited. The process further includes depositing an interlevel dielectric layer (58), dry etching the interlevel dielectric layer (58) to thin the interlevel dielectric layer (58) and, optionally, depositing additional interlevel dielectric layer (58') material to achieve a preselected thickness. A second patterned metallization layer (64) is deposited over the interlevel dielectric layer ( 58/58').

Abstract: Thin file transistor including polycrystalline silicon or amorphous silicon thin film channel regions having a thickness of between about 100 .ANG. and 2500 .ANG. which are thinner than at least a portion of the source and drain regions and active matrix assemblies including thin film transistors for improved electro-optical displays are provided.

Abstract: A semiconductor device includes a buried impurity layer (3) formed at a predetermined depth from a main surface of a semiconductor substrate (1) by utilizing ion injection of a conductivity type determining element, and a gettering layer (2) formed in a position adjacent to and not shallower than the buried impurity layer (3) by utilizing ion injection of an element other than a conductivity type determining element.

Abstract: An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first metal electrode, a first antifuse dielectric layer, preferably silicon nitride, disposed on the lower first electrode and an antifuse layer, preferably amorphous silicon, disposed on the first dielectric layer. An inter-layer dielectric layer is disposed on the antifuse layer and includes an antifuse via formed completely therethrough. A second antifuse dielectric layer, preferably silicon nitride, is disposed over the amorphous silicon layer in the antifuse via, and an upper second metal electrode is disposed over the second dielectric layer in the antifuse via.

Abstract: A semiconductor device has a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type contacted by respective first and second electrodes. A semi-insulating layer extends between the first and second electrodes and there is a first insulating layer between the semi-insulating layer and the first semiconductor region. The sheet resistivity of the semi-insulating layer varies, and this improves the high breakdown voltage of the p-n junction of the semiconductor device between the first and second semiconductor layers, by acting as a shield for charges included on a passivation insulation layer covering the semi-insulating layer and the first and second electrodes. Third semiconductor regions, with corresponding third electrodes, extend around, and are spaced from, the second semiconductor region.

Abstract: A resin molded type semiconductor device has a metallic guard ring that is formed to cover the peripheral edge of the surface of a tetragonal semiconductor substrate. In order to prevent a passivation film on the guard ring from being cracked by stresses due to a resin mold package concentrating in the four corners of the semiconductor substrate, slits or rows of small holes are formed in the corner portions of the guard ring.