Abstract: A manufacturing method for a semiconductor device, wherein a polyimide-based resin layer is covered with a P-CVD oxide silicon film or the like before it is subjected to degassing process in order to prevent blisters or cracks of a cover film of a semiconductor device which has the polyimide-based resin layer as an interlayer insulating film. This makes it possible to take the semiconductor device out in open air after the degassing process and to prevent the dispersion of reaction products resulting from amidation during the degassing process.

Abstract: Various methods are described for analyzing an electronic circuit formed upon a frontside surface of a semiconductor substrate having opposed frontside and backside surfaces. Each method includes forming a layer of an antireflective coating material upon the backside surface of the substrate prior to detecting electromagnetic radiation emanating from the backside surface. The layer of an antireflective coating material reduces reflections which contribute to background noise levels. As a result of reduced background noise levels, the detection capabilities of the methods and the resolutions of any scanned images produced using the methods are improved. A first method includes forming a layer of an antireflective coating material upon the backside surface of the substrate, directing a beam of electromagnetic radiation toward the backside surface of the substrate, and detecting an electrical response from the electronic circuit.

Abstract: A hydrogen plasma downstream treatment equipment comprises a first gas supply source for supplying a hydrogen gas, a second gas supply source for supplying a nitrogen fluoride gas, and a tube-like chamber used for surface treatment of a semiconductor layer by use of the hydrogen gas and the nitrogen fluoride gas. The chamber includes a plasma generator for activating the hydrogen gas and the nitrogen fluoride gas by introducing the nitrogen fluoride gas in which a flow rate ratio of the hydrogen gas and the nitrogen fluoride gas is in excess of 4, a processor placed in a downstream of the plasma generator to place the semiconductor layer therein, and gas flow controlling means for controlling the first gas supply source and the second gas supply source so as to set a flow rate of the nitrogen fluoride gas four times a flow rate of the hydrogen gas.

Abstract: A method of fabricating a MOS-gated semiconductor device in which arsenic dopant is implanted through a mask to form a first layer, boron dopant is implanted through the mask to form a second layer deeper than the first layer, and in which a single diffusion step diffuses the implanted arsenic and the implanted boron at the same time to form a P+ body region with an N+ source region therein and a P type channel region.

Abstract: A novel design of an oxidation mask for improved control of birds beak and more specifically for tailoring and smoothing the field oxide isolation profile in the vicinity of the birds beak. The mask design is particularly advantageous for narrow field isolation spacings found in sub half-micron integrated circuit technology. The mask uses a thin tapered silicon nitride foot along its lower edge to allow nominal expansion of the oxide during the early stages of oxidation, thereby permitting in-situ stress relief as well as a smoothing of the oxide profile. The taper of the foot provides a gradual increase in mask stiffness as oxidation proceeds under the mask edge, allowing greatest flexibility during the early rapid growth period followed by increasing stiffness during the later stages when the growth rate has slowed, thereby inhibiting the penetration of birds beak. Shear stresses responsible for dislocation generation are reduced by as much as fifty fold.

Abstract: An interlayer insulating film made of insulating material is deposited on a substrate having a conductive region at least partially on the surface area thereof. A connection hole is formed through the interlayer insulating film, to expose the conductive region. The connection hole is filled with a plug made of conductive material. An underlying layer made of Ti is deposited over the whole surface of the substrate including the surface of the plug. A wiring layer made of Al alloy is deposited on the underlying layer, without exposing the substrate to the external atmosphere after the deposition of the Ti layer. The wiring layer is reflowed by heating the substrate. A method is provided which is capable of connecting an upper wiring layer to a lower conductive region without lowering resistance to electromigration and lowering step coverage.

Abstract: The present invention comprises a metallization method that forms a three-level interconnect in an electrical circuit. The method comprises providing a substrate assembly and depositing thereon a first dielectric layer thereover. A second dielectric layer is then deposited over the first dielectric layer. The second dielectric layer is patterned and anisotropically etched to form contact corridors. The second dielectric layer is again patterned and etched to form trenches, some of which are immediately above the contact corridors. An electrically conductive material is deposited to fill the contact corridors and trenches, and to leave a portion of the electrically conductive material above the second dielectric layer and directly above both the contact corridors and the trenches. The deposition forms a unitary three-level interconnect having a contiguous trench below a contact corridor below a metal line, where the metal line is above the second dielectric layer.

Abstract: Two steps of planarizing are performed during isolation trench fabrication resulting in a more uniform planarization of an integrated circuit substrate. A protective layer deposition and a planarizing step are performed prior to a final planarizing step. Applying protective material fills in a portion of recesses in a dielectric layer overlying isolation trench areas. A first global planarization process eliminates narrower recesses and shallows out deeper recesses without causing dishing in the dielectric material. Much of the protective material is removed by the first global planarization process. The remaining protective material is stripped. A final global planarization process then is performed which removes dielectric material outside of the trench areas. A well-defined border of the trenches results.