Patents Examined by Jack A. Lane
  • Patent number: 7434002
    Abstract: In a method of optimizing utilization of a shared cache, a set of locations in the cache is probed. The probing takes place while an observed process is running, descheduled, or interrupted. It is determined which portions of the cache are utilized by the observed process. Utilization of the cache is optimized based on result of the determination of which portions of the cache are utilized by the observed process.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: October 7, 2008
    Assignee: VMware, Inc.
    Inventors: John Zedlewski, Carl Waldspurger
  • Patent number: 7428624
    Abstract: Provided is a computer system including a plurality of data storage apparatus and manages a bandwidth of a data storage apparatus according to an attribute of a storage volume. A storage system includes an interface for processing access to the storage volume from a host computer, and a control unit for controlling allocation of the storage volume to the host computer. A management computer transmits a request of setting a bandwidth to be accessed by the host computer via the interface in the storage volume to the storage system. The control unit sets the bandwidth corresponding to a ratio of processing access to each storage volume in the storage system based on the request from the management computer, and allocates the storage volume having the bandwidth requested by the host computer set therein to the host computer to be accessed by the host computer to the allocated storage volume.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: September 23, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Fumi Fujita, Masayuki Yamamoto, Naoko Maruyama, Yasunori Kaneda
  • Patent number: 7428617
    Abstract: A cache memory includes a first-level cache-memory unit that stores data; a second-level cache-memory unit that stores data that is same as the data stored in the first-level cache-memory unit; a storage unit that stores a part of information relating to the first-level cache-memory unit; and a coherence maintaining unit that maintains cache-coherence between the first-level cache-memory unit and the second-level cache-memory unit based on information stored in the storage unit.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: September 23, 2008
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Okawa, Kumiko Endo, Hiroyuki Kojima, Masaki Ukai
  • Patent number: 7426606
    Abstract: A device includes a processor connected to a memory. The device further includes a module having a process. The module is integrated in a Multimedia File Manager (MFM). The process operates to allow an external computer access to MFM volumes in the memory. A method includes reverting a file allocating table (FAT) cluster number to a file ID and file offset of a non-FAT flash memory file system.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: September 16, 2008
    Assignee: Intel Corporation
    Inventor: He Chu
  • Patent number: 7424573
    Abstract: An information processing apparatus reads and writes information in a plurality of recording media is provided. The apparatus includes a formatting determination section which, in the case of formatting the recording media, determines whether or not the recording media are to be formatted by handling the recording media as an integrated recording medium, and an integrated formatting section which, when the formatting determination section determines that the recording media are to be formatted by handling the recording media as the integrated recording medium, formats the recording media by handling the recording media as the integrated recording medium.
    Type: Grant
    Filed: August 1, 2006
    Date of Patent: September 9, 2008
    Assignee: Sony Corporation
    Inventors: Ryogo Ito, Fumihiko Kaise
  • Patent number: 7424591
    Abstract: A computer implemented method, data processing system, and computer usable program code are provided for storing data items in a computer. A plurality of hash functions of data values in a data item are computed. A corresponding memory location is determined for one of the plurality of hash functions. The data item and a key portion and a payload portion of all data items are stored contiguously within the memory location. Also provided for are retrieving data items in a computer. A plurality of hash functions of data values in a probe key are computed. A corresponding memory location is determined for each of the plurality of hash functions. Data items in each memory location are examined to determine a match with the probe key. Responsive to a match, a payload of the matching stored data item is returned. All of the steps are performed free of conditional branch instructions.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: September 9, 2008
    Assignee: International Business Machines Corporation
    Inventor: Kenneth Andrew Ross
  • Patent number: 7424587
    Abstract: A method for writing data to a solid-state disk having a first portion of solid-state memory of a volatile nature and a second portion of solid-state memory of a non-volatile nature, and a controller for controlling data operations to the memory includes acts of (a) receiving at the controller, write data for writing to an assigned address in non-volatile memory; (b) determining at the controller if there is existing data associated with a write address in volatile memory, the write address referencing the assigned address in volatile memory; and (c) upon finding data in volatile memory held for the assigned write address or not at act (b), writing the data into the volatile memory at a predestinated write address in volatile memory.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: September 9, 2008
    Assignee: Dataram, Inc.
    Inventors: Jason Caulkins, Michael Richard Beyer
  • Patent number: 7421534
    Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: September 2, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Hitoshi Kurosawa
  • Patent number: 7418544
    Abstract: A system, method, computer program and article of manufacture for updating a disk that moves updates for a specific database object into available contiguous free data blocks, and writes the multiple updates to disk using a single disk access, maintaining database transactional and durability semantics.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: August 26, 2008
    Assignee: Oracle International Corporation
    Inventors: Niloy Mukherjee, Amit Ganesh
  • Patent number: 7415583
    Abstract: A method and apparatus to free at least a portion of memory space of a memory device from at least a portion of a stored data block, wherein the freeing is based on the block sequence number of the stored data block and a quality indicator value related to at least a portion of the stored data block. The apparatus may include a receiver to receive at least the portion of the data block transmitted according to an error correction scheme.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: August 19, 2008
    Assignee: Marvell World Trade Ltd.
    Inventors: Moti Altahan, Sharon Levy
  • Patent number: 7415570
    Abstract: A tape drive apparatus includes a data transfer apparatus for transferring data to and from a tape media loaded in the tape drive apparatus, a first port for communicating with the data transfer apparatus in a tape drive mode, a second port for communicating with the data transfer apparatus in an optical storage device mode, and an emulation apparatus for permanently emulating an optical storage device at the second port for enabling an external device to access the data transfer apparatus, via the second fort, in the optical storage device mode.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: August 19, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Rhys Wyn Evans, Alastair Michael Slater, Duncan Wakelin
  • Patent number: 7412568
    Abstract: Methods, apparatus, and systems are provided for caching. A caching process is automatically modified in response to update eligibility and an interference relation for a plurality of threads. Data is read into a cache, and a reference to the data is provided to a plurality of threads. An initial thread receives a signal from a last thread once the last thread has the reference to the data. The initial thread, in response to the signal, modifies the data and updates changes to the data within the cache and then sends another signal to a next thread, indicating that the next thread may now perform a volatile operation on the data within the cache.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Jinquan Dai, Long Li
  • Patent number: 7409495
    Abstract: Methods, systems, and computer program products to provide temporal storage in a fabric-based virtualization environment are presented. Such capacity is provided through the association of a temporal storage appliance, which is configured as a member of a linked VLUN with a non-temporal disk volume. The linked VLUN is provided by a virtualizing fabric switch to a network node such as a network node.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: August 5, 2008
    Assignee: Symantec Operating Corporation
    Inventors: Anand A. Kekre, Ankur P. Panchbudhe, Vrijendra S. Gokhale
  • Patent number: 7409515
    Abstract: A method of data exchange between volumes without using any unnecessary resource in a storage system includes allocating cache areas for data exchange on a memory, determining the location of data to be exchanged, reading out data from the determined location in source and destination volumes and storing data in their respective caches, and writing data stored in the cache to thus determined location of the volume different from the one that the data was read out.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: August 5, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Hanai, Akihiko Sakaguchi
  • Patent number: 7406566
    Abstract: A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments of the invention include a plurality of cache agents that each communication with the same protocol agent, which may or may not be integrated within any one of the cache agents. Embodiments of the invention also include protocol agents capable of storing multiple sets of data from different sets of cache agents within the same clock cycle.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventor: Benjamin Tsien
  • Patent number: 7404031
    Abstract: A nonvolatile semiconductor memory includes a storage area including of a plurality of data blocks and a management block which stores management information related to a storage medium in a lump. The storage area is divided into a plurality of areas and each area has a data block containing a particular page which stores information indicating whether or not the management block is present in the area.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: July 22, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takashi Oshima
  • Patent number: 7404058
    Abstract: A method and apparatus for enqueuing and dequeuing packets to and from a shared packet memory, while avoiding collisions. An enqueue process or state machine enqueues packets for a communication connection (e.g., channel, queue pair, flow). A dequeue process or state machine operating in parallel dequeues packets and forwards them (e.g., to an InfiniBand node). Packets are stored in the shared packet memory, and status/control information is stored in a control memory that is updated for each packet enqueue and packet dequeue. Prior to updating the packet and/or control memory, each process interfaces with the other to determine if the other process is active and/or to identify the other process' current communication connection. If the enqueue process detects a collision, it pauses (e.g., for a predetermined number of clock cycles). If the dequeue process detects a collision, it selects a different communication connection to dequeue.
    Type: Grant
    Filed: May 31, 2003
    Date of Patent: July 22, 2008
    Assignee: Sun Microsystems, Inc.
    Inventors: John M. Lo, Charles T. Cheng
  • Patent number: 7404036
    Abstract: Provided are a method, system, and article of manufacture, where a plurality of extents are stored in a first set of storage units coupled to a controller. A determination is made that a second set of storage units has been coupled to the controller. The plurality of extents are distributed among all storage units included in the first set of storage units and the second set of storage units.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: July 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Joseph Smith Hyde, II, Bruce McNutt
  • Patent number: 7401182
    Abstract: A method for personalizing the working of a portable communication device (1) including the steps of an initialization step (A0) during which multimedia content data files are stored (A01) in a removable memory (18) of said portable communication device, and personalization parameters for controlling peripherals (2, 17) of said device are set (A02) with software links to at least some of said data files; and further including prior to removal of said removable memory (18), a step (A03) for creating a table including said software links, and a step (A2) for copying, according to said table, said data files for which software links exist or at least a transformation of said data files, from said removable memory (18) to an internal memory (7) of said portable communication device.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: July 15, 2008
    Assignee: T & A Mobile Phones Limited
    Inventors: Minh Le, Carole Fagnoni
  • Patent number: 7401183
    Abstract: A system for authenticating a memory card including: a memory card host device including a plural area authentication module which judges whether the memory card has plural storage areas, and an area switching module which switches a storage area subject to access a different storage area from among plural storage areas; a memory card including plural storage areas, at least one internal register which retains a value indicating the number of storage areas, and a controller which transmits the value indicating the number of the storage areas to the memory card host device; and a bus which transmits and receives data between the memory card host device and the memory card.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: July 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takaya Suda