Abstract: Systems and methods for providing data modification operations in memory subsystems. Systems include a plurality of memory devices, a memory controller, one or more memory busses connected to the memory controller and a memory hub device. The memory controller receives and responds to memory access requests including memory update requests from a processor. The memory controller also generates a memory update command in response to receiving a memory update request. The memory hub device includes a first port, a second port and a control unit. The first port is in communication with the memory controller via one or more of the memory busses for transferring data and control information between the memory hub device and the memory controller. The second port is in communication with one or more of the memory devices.

Abstract: Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag miss allocation. Herein, steps and instructions provide for forming a first-in, first-out (FIFO) cache way listing of victim ways for the cache memory, wherein the depth of the FIFO cache way listing approximately equals the number of ways in the cache memory. The method and system place a victim way on the FIFO cache way listing only in the event that a tag miss results in a tag miss allocation, the victim way is placed at the tail of the FIFO cache way listing after any previously selected victim way. Use of a victim way on the FIFO cache way listing is prevented in the event of an incomplete prior allocation of the victim way by, for example, stalling a reuse request until such initial allocation of the victim way completes or replaying a reuse request until such initial allocation of the victim way completes.

Abstract: In a method of utilizing cache metadata to optimize memory access, cache metadata associated with a set of cache locations is inspected by software. The cache metadata is analyzed to determine memory utilization. Memory access is optimized based on results of the analysis of the cache metadata.

Abstract: Systems and methods for providing distributed autonomous power management in a memory system. Embodiments include a memory system for storing and retrieving data for a processing system. The memory system includes a memory controller for receiving and responding to memory access requests, a memory bus in communication with the memory controller, a plurality of memory devices, and a control unit external to the memory controller. The memory devices are in communication with the memory controller via the memory bus, with one or more of the memory devices being associated with a group. The control unit autonomously manages power within and for the group of memory devices.

Abstract: Use of storage access keys is facilitated to enable flexible control of storage access. Any selected storage access key is usable to access storage. Storage access keys may be specified in user registers and can override storage access keys indicated in system registers.

Abstract: An apparatus, system, and method are disclosed for integrating a blade RAID controller and storage. A storage blade enclosure communicates with a blade chassis. The storage blade enclosure is mounted within the blade chassis. A RAID controller disposed in the storage blade enclosure receives a command through the storage blade enclosure. In one embodiment, the command is communicated through the blade chassis from a processor blade mounted in the blade chassis. The RAID controller redundantly stores data to or retrieves data from a storage module disposed in the storage blade enclosure in response to the command using a RAID redundancy methodology.

Abstract: A method, system, apparatus, and computer-readable medium are provided for synchronizing I/O operations in a computer system. According to aspects of the invention, multiple reader and writer locks are provided that may be acquired by calling processes at two different granularities. Locks may be acquired for an area of storage equivalent to the logical unit of allocation or for a sub-provision area equivalent to a unit of snapshot read-modify-write. Each lock is represented by a lock data structure that represents the same amount of logical address space as the logical unit of allocation. A request that arrives to the lock data structure is made to wait in a lock wait queue until the request can be honored. Requests that have been honored but that have not yet released the lock are maintained in a dispatch queue. When a writer lock is assigned to a lock request, no other readers or writers may be allocated to it.

Abstract: In a method of synchronizing with a separated disk cache, the separated cache is configured to transfer cache data to a staging area of a storage device. An atomic commit operation is utilized to instruct the storage device to atomically commit the cache data to a mapping scheme of the storage device.

Abstract: Systems and methods are disclosed herein for retrieving data from memory in a computer system. In one example, a memory controller is coupled to a system bus in a computer system that includes bus masters similarly coupled to the system bus. The memory controller is configured to receive requests to read or write data from memory from bus masters of the computer system. If the memory controller receives an initial request from certain bus masters, the memory controller is further configured to anticipate a future request from certain bus masters and prefetch data on behalf of certain bus masters for rapid delivery following a subsequent request to read data from memory submitted by the certain bus masters.

Abstract: A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.

Abstract: In one embodiment, the present invention includes a method for maintaining data in a first level cache non-inclusively with data in a second level cache coupled to the first level cache. At the same time, at least a portion of directory information associated with the data in the first level cache may be maintained inclusively with a directory portion of the second level cache. Other embodiments are described and claimed.

Abstract: A blade enclosure is provided which may accommodate a first configuration which includes integrated drive enclosure blades (I-DEBs) or a second configuration which includes I-DEBs and non-integrated or switched DEBs (S-DEBs). Each I-DEB includes a pair of redundant RAID controllers, each having two configurable ports. In the first configuration, all four ports are configured as host adapter (HA) ports through which data is exchanged with server blades. In the second configuration, one port of each RAID controller is configured as an HA port, through which data is exchanged with server blades, and the other port of each RAID controller is configured as a device adapter (DA) port, through which data may be exchanged with the S-DEB. Zones may also be established to separate traffic between the servers and the I-DEB from traffic between the I-DES and the S-DEB.

Abstract: A hierarchical storage system includes file servers and a policy engine server. Offline attributes are added to file system inodes in a primary file server, file system parameters are added in the primary server, offline read and write access method fields are added to a connection database, and the primary file server uses these attributes and parameters for selecting a particular read method or write method for access to an offline file or section of an offline file. The write methods follow a “write recall full” policy, a “pass-through write” policy, a “pass-through multi-version” policy, or a “directory write pass-through” policy. The pass-through multi-version policy results in a new offline version of a file each time that a client opens and writes to a multi-version file. The directory write pass-through policy results in a new offline file when a file is created within a write pass-through directory.

Abstract: An apparatus, system, and method are disclosed for integrating redundant array of independent disk (“RAID”) storage within a blade center. A plurality of mutually autonomous storage subsystems mount within the blade center through a switch. Each storage subsystem includes a storage module comprising a plurality of storage devices and a RAID controller. A server blade mounted within the blade center may access a first storage subsystem through a switch module. The switch module is a non-blocking, cross-point switch. In one embodiment, the switch module restricts the server blade's access to a second storage subsystem.

Abstract: A read-write snapshot copy facility is constructed from a hierarchical storage management facility. The read-write snapshot copy file system initially comprises stub files pointing to the files in a read-only snapshot copy file system. When an application writes to a file in the read-write snapshot copy, the read-write snapshot copy facility migrates a copy of the file to replace the stub file, and then writes to the migrated file. Because the read-write snapshot copy facility references the files in the read-only snapshot file system in a network namespace using standard protocols such as NFS or CIFS, the read-write snapshot copy facility permits referencing of distributed read-only snapshot file systems in an open (heterogeneous) network environment, and the read-write snapshot copy is scalable by linking the read-write snapshot copy facility to multiple file servers containing read-only snapshot file systems.

Abstract: A system and method for address space layout randomization (“ASLR”) for a Windows operating system is disclosed. The address space layout includes one or more memory regions that are identified and then a particular implementation of the system randomizes the identified memory region in order to prevent any software vulnerabilities.

Abstract: A method for pipelining a memory in an integrated circuit includes providing a first clock phase and providing a second clock phase, wherein the first clock phase and the second clock phase are at least partially non-overlapping. The method further includes providing a first memory array and providing a second memory array, wherein the second memory array shares a wordline with the first memory array. The method further includes using said wordline to select at least one row of the first memory array during the first clock phase. The method further includes using said wordline to select at least one row of the second memory array during the second clock phase.

Abstract: A storage apparatus is provided with a storage area for storing data sent from a host computer, and a virtual/logical volume to which a dynamically variable storage area is allocated from within the storage area, the volume being provided to the host computer, and this storage apparatus is configured to include: a pool area generation unit for generating a plurality of pool areas composed from the storage area; a setting unit for setting, for each of the plurality of pool areas generated by the pool area generation unit, an allocation unit size for allocating a storage area from within the storage area provided by the pool area to the virtual/logical volume; a selecting unit for selecting, when data to be stored in the storage area is sent from the host computer, a pool area from among the plurality of pool areas having the allocation unit size set by the setting unit, in accordance with the size of the sent data; and an allocation unit for allocating a storage area from within the storage area provided by th

Abstract: A memory controller controlling a plurality of semiconductor memory devices includes a refresh control circuit controlling refresh operations of the semiconductor memory devices according to positional information of memory chips of the memory devices. The refresh control circuit classifies the semiconductor memory devices into first and second groups and sets an auto refresh interval of the semiconductor memory devices belong to the first group and an auto refresh interval of the semiconductor memory devices belong to the second group different from each other.

Abstract: Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.