Abstract: A reliable file system method and system are provided. The reliable file system substantially ensures that an on-media state of a file system is maintained while another working-media state of the file system is modified. At a transaction point, issued by a computer system associated with the file system, the working-media state of the file system is written completely to non-volatile storage associated with the file system. Once the write process is complete, the on-media state of the file system is updated.
Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. During a third mode of operation, a first plurality of storage cells in a first row of storage cells in a first memory bank is accessible in response to a first column address.
Type:
Grant
Filed:
September 30, 2004
Date of Patent:
October 9, 2007
Assignee:
Rambus Inc.
Inventors:
Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
Abstract: In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.
Abstract: A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.
Type:
Grant
Filed:
March 22, 2005
Date of Patent:
October 2, 2007
Assignee:
Intel Corporation
Inventors:
Christopher J. Shannon, Mark Rowland, Ganapati Srinivasa
Abstract: A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
Type:
Grant
Filed:
October 29, 2004
Date of Patent:
October 2, 2007
Assignee:
International Business Machines Corporation
Inventors:
Kevin C. Gower, Mark W. Kellogg, Warren E. Maule, Thomas B. Smith, III, Robert B. Tremaine
Abstract: A scheduler to manage the reading activity of a plurality of read hubs is described. Each read hub is capable of reading a piece of a packet from a different memory bank within a same cycle of operation so that pieces of different packets can be read from the memory banks within the same cycle of operation. The scheduler: 1) defines each read hub as an active read hub or inactive read hub, wherein an active read hub is engaged to read at least one packet from the memory banks and an inactive read hub is not so engaged; 2) defines each active read hub as a low speed mode read hub or a high speed mode read hub, wherein, a first packet read by a high speed mode read hub is read from the memory banks at a faster rate than a second packet read by a low speed mode read hub; and, 3) dynamically changes the number of active read hubs, the number of low speed mode read hubs and the number of high speed mode read hubs in light of traffic conditions.
Type:
Grant
Filed:
May 7, 2003
Date of Patent:
September 11, 2007
Assignee:
Avago Technologies General IP (Singapore) Pte. Ltd.
Inventors:
Rick Reeve, Richard L. Schober, Ian Colloff
Abstract: A memory device system of the present invention is equipped with a memory device comprising a first memory unit for storing data, and a second memory unit for storing an access log regarding an access to the first memory unit; a port for inputting and outputting data; a control device for writing the access log in a memory area other than the area, where the access log is already written in the second memory unit, if an access request to the first memory unit is input through the port and the access log is written in the second memory unit according to the access request, and for prohibiting a write in the second memory unit if an information write request in the second memory unit is input through the port.
Abstract: A system for authenticating a memory card including: a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card; a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device; and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card.
Abstract: Synthesized backup set catalogs are created to more efficiently create synthetic full backups of a data volume or to more efficiently restore a data object of the data volume. In one embodiment, the synthesized backup set catalog comprises n entries corresponding to n data objects, respectively, of a data volume being backed up. The synthesized backup set catalog can be created with the creation of an incremental backup of the data volume. Each entry of the synthesized backup set catalog may contain a backup identification (ID), wherein each backup ID identifies at least one of two backup sets of the data volume.
Abstract: The storage area of a storage unit includes a file area and temporary write area. A pair of map tables are allocated in the storage area. An update processing unit executes update of a page in a file stored in a file area by writing updated data to an unused page acquired from a temporary write area. A commit module alternately writes a list of effective pages in the temporary write area to the pair of map tables whenever each of transactions is committed. A checkpoint processing unit writes back the updated data of each effective page in the temporary write area to the corresponding original page position in the file area.
Abstract: An apparatus and method for managing a memory of a computer and controlling a booting operation of the computer, are provided. The computer includes a memory having a user area and a protected security area (PSA). The user area has a management area. The method includes assigning a first partition to the user area of the memory; storing first partition information in the management area of the user area, the first partition information pertaining to the first partition; assigning a second partition to the PSA in response to an access signal, the access signal authorizing access to the PSA; storing, in the management area, second partition information pertaining to the second partition; storing the second partition information in the PSA; and removing the second partition information from the management area after storing the second partition information in the PSA.
Type:
Grant
Filed:
August 9, 2004
Date of Patent:
August 28, 2007
Assignee:
LG Electronics Inc.
Inventors:
Hyung Guk Han, Byung Chuel Kim, Jae Ung Han, Do Gwang Rha
Abstract: A data storage system has data storage devices dispersed over a geographic area such that any two of the data storage devices are separated by a distance measured in miles or kilometers. A processing system coupled to the data storage devices performs several functions that culminate in the generation of a data package for each data bit of a data file that is to be stored. Each such data package includes a value of the data bit, a bit storage location, identification of the data file with which the data bit is associated, and an ordered-position bit number associated with the data bit. The data processing system distributes data packages associated with a data file approximately evenly amongst the data storage devices for storage thereat.
Type:
Grant
Filed:
May 17, 2004
Date of Patent:
August 28, 2007
Assignee:
United States of America as represented by the Secretary of the Navy
Abstract: A system provides mechanisms and techniques to retrieve trace data from a trace buffer residing in a data storage system. The software program operating on a processor within the data storage system operates in trace mode to produce trace data in the trace buffer upon occurrence of trace events. An event trace routine operates in response to a system call to access the trace buffer and return either a current value of a trace buffer pointer or the current trace buffer pointer as well as trace data read from the trace buffer beginning at a location and in an amount as specified in the system call to the event trace routine. The trace capture process can operate either within the data storage system or preferably on a remote host computer system to access trace data in the trace buffer in the data storage system by using the event trace routine.
Type:
Grant
Filed:
November 1, 2004
Date of Patent:
August 21, 2007
Assignee:
EMC Corporation
Inventors:
William Zahavi, Andrew M. Shooman, Yeshayahu Hass
Abstract: A system for loosely coupled temporal storage management includes a logical storage aggregation including a plurality of data blocks, a data producer, one or more data consumers, and a temporal storage manager. The temporal storage manager may be configured to maintain a producer shadow store including entries stored in a log-structured logical volume, where each entry is indicative of one or more data blocks of the logical storage aggregation that have been modified by the data producer. The temporal storage manager may also be configured to maintain a repository containing a baseline version of the logical storage aggregation, and to provide the data consumers with read-only access to the producer shadow store and the repository.
Abstract: A log-structured temporal shadow store may comprise a logical storage aggregation including a plurality of blocks, a log-structured storage device, and shadow management software. The log-structured storage device may include a plurality of log entries, where each log entry includes one or more modified blocks of the logical storage aggregation and an index to the modified blocks. In response to a new batch of changes to the logical storage aggregation, the shadow management software may be configured to append a new log entry to the log-structured storage device, including newly modified blocks and an index to the newly modified blocks. The index may be organized as a modified B+ tree, and the log-structured storage device may be a logical volume, such as a mirrored logical volume.
Abstract: Provided are a method, system, and article of manufacture, wherein a request is received for switching a logical volume from one state to another state, wherein the logical volume is in a mirrored state if data corresponding to the logical volume is mirrored from a first storage to a second storage, and wherein the logical volume is in a non-mirrored state if the data corresponding to the logical volume is not mirrored from the first storage to the second storage. A determination is made as to whether to perform the switching, in response to receiving the request.
Type:
Grant
Filed:
March 31, 2005
Date of Patent:
August 7, 2007
Assignee:
International Business Machines Corporation
Inventors:
Shah Mohammad Rezaul Islam, Thomas Charles Jarvis, Matthew Joseph Kalos, Robert Akira Kubo
Abstract: Computer system for electronic data processing having programmable data transfer units used for transferring data from a first memory in which data is stored in a form of a multi-dimensional array to a second memory in such a way, that spatial or temporal locality for the transfer is established.
Abstract: A file system for streaming media uses at least one set of a plurality of storage bands that are arranged sequentially on a magnetic storage disk. Each storage band contains a plurality of storage blocks. At least one data file that is formed from a plurality of sequential data blocks and contains, for example, media content and/or video data is stored in a set of storage bands so that each data block of the data file is stored in a sequential manner with respect to consecutively sequential data blocks. The plurality of storage blocks contained in each storage band are sequentially arranged in the storage band and the storage blocks contained in each storage band sequentially store data blocks of the data file.
Type:
Grant
Filed:
June 23, 2004
Date of Patent:
August 7, 2007
Assignee:
International Business Machines Corporation
Abstract: A method and system for tracking usage of memory in a computer system is provided. Arguments for both the size of a memory allocation and the type of memory being allocated are reserved in a fixed location. A first fixed location is reserved for small memory allocations, i.e. less than one page, and a second fixed location is reserved for large memory allocations, i.e. one page or larger. The fixed location is selected based upon a determination of the size of an allocation required by a calling application. Upon receipt of a memory allocation request by the calling application, a pointer is returned to the calling application identifying the fixed location. Similarly, upon release of memory by the calling application, a counter is decremented to track the amount of memory in use by the application.
Type:
Grant
Filed:
June 15, 2004
Date of Patent:
July 24, 2007
Assignee:
International Business Machines Corporation
Abstract: An archival cartridge management system for conditioning removable data cartridges and normal archival operations is disclosed. The archival cartridge management system includes a cartridge holder and a controller. The cartridge holder has a connector configured for coupling to a removable data cartridge. The connector is coupled to the controller, which performs archival functions on removable data cartridges. The controller reads from removable data cartridges to determine if at least some data stored on a removable data cartridge should be refreshed. If so, the controller refreshes data stored on the removable data cartridge.