Abstract: A method and apparatus to free at least a portion of memory space of a memory device from at least a portion of a stored data block, wherein the freeing is based on the block sequence number of the stored data block and a quality indicator value related to at least a portion of the stored data block. The apparatus may include a receiver to receive at least the portion of the data block transmitted according to an error correction scheme.

Abstract: A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.

Abstract: A file to be written can be partitioned into one or more partitions. Each such input partition is identified with a hash code and a group ID. Replica(s) of an input partition can be created to ensure a certain number of identical partitions. When a file is accessed, each partition that is read out can be checked for corruption. Corrupted readout partitions are then replaced with a validated replacement partition, whether the replacement partition is from a replica or from another file.

Abstract: Disclosed is a method and apparatus for tracking in-progress writes to a data volume and a copy thereof using a multi-column bit map. The method can be implemented in a computer system and, in one embodiment, includes creating a data volume in a first memory, and creating a copy of the data volume in a second memory. In response to the computer system receiving a request to write first data to the data volume, the computer system switches the state of first and second bits of a map entry in a memory device, wherein the state of the first and second bits are switched using a single write access to the memory device.

Abstract: A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the comparand register of the CAM device, the matching entry's counter may be incremented. Alternatively, if there are multiple matching entries, in some instances only one matching entry has its counter incremented. The counter value can be written or read as part of either the least significant or most significant bits of the CAM entry.

Abstract: A data relay controller for decreasing operation load and reducing circuit scale. The controller transfers a data block between a buffer memory and a computer. An access circuit writes the main data to or reads the main data from the buffer memory. An address generation circuit generates address data in accordance with a writing or reading head address of the main data provided from an external device. A counter counts the main data to generate a count value. An address skip control circuit skips the address data by a predetermined number of addresses corresponding to a storage area of the sub data or the parity data in the buffer memory in accordance with the count value and the head address.

Abstract: A silent mirroring protocol is provided, which eliminates the arbitration/selection times associated with all nexuses after the first nexus. During the initial SCSI bus negotiation, the initiator determines the transfer mode capability of all targets. The initiator establishes a group identification. Participants of the group recognize the group and look for an individual identification within the group. The initiator performs arbitration/selection with attention to the leader of the group. The initiator uses a message out phase with a vendor command to select a participant for a data block transfer. Each participant snoops the bus and recognizes when it is the target. If the initiator has more data to mirror, the process is repeated. When the last data block is transferred, the initiator sends a message out to the last participant, which is interpreted by the target leader as a command to release the bus. Each participant reselects the nexus initiator and returns a status.

Abstract: A method and apparatus to improve the read/write performance of a hard drive is presented. The hard drive includes solid state, non-volatile (NV) memory as a read/write cache. Data specified by the operating system is stored in the NV memory. The operating system provides a list of data to be put in NV memory. The data includes data to be pinned in NV memory and data that is dynamic. Pinned data persists in NV memory until the operating system commands it to be flushed. Dynamic data can be flushed by the hard drive controller. Data sent by an application for storage is temporary stored in NV memory in data blocks until the operating system commits it to the disk.

Abstract: A network attached storage device (“NASD”), where that NASD is capable of communicating with one or more host computers, and where that NASD is capable of communicating with one or more data storage and retrieval systems. The network attached storage device includes an information storage device, a first file system driver, where that first file system driver is in communication with the information storage device, and a second file system driver, where that second file system driver is in communication with the first file system driver. The network attached storage device further includes a plurality of first computer files stored on the information storage device, and a plurality of second computer files, where one or more of the plurality of first computer files comprises two or more of the plurality of second computer files.

Abstract: A method of enabling a hardware module to interact with a data structure is disclosed. The method comprises the steps of enabling the hardware module to determine an address of a data item referenced by the data structure; providing a base address for the data structure to the hardware module; and accessing a data item referenced by the data structure. A field programmable gate array having a hardware module capable of interacting with a data structure is also described. The field programmable gate array comprises a memory having a data structure; a hardware module coupled to the memory and comprising a lookup table; and a target address generated by the hardware module for a data item of the data structure.

Abstract: A system and method is provided for interleaving data in a communications device. The system includes a memory for storing symbols of a data block, a read module and a write module, each of which is coupled to the memory. The system also includes a interleaving logic module coupled to the read and write modules. The interleaving logic module determines an interleaving sequence comprising a sequence of memory addresses. Each memory address is then communicated sequentially to the read and write modules. When the read module receives the address, the read module reads the stored data symbol. When the write module receives the address, the write module writes a symbol from a next data block to the vacated address. The interleaving logic module repeats these steps until every symbol of the stored block has been read and every symbol of the next data block has been written to memory.

Abstract: A method and system for allowing flexible control of access to a shared memory by multiple requesters. In a preferred embodiment, the invention arbitrates access to flash memory on a HBA between multiple host channels and HBA microprocessors, and eliminates contention possibilities for the flash during write cycles by the allowing a grant to be locked for a period defined by the flash write protocol and timing.

Abstract: A method and system of increasing the speed of a write barrier check. Instead of using zero null references, in one embodiment of the invention a special object is created at a valid and globally accessible location in memory. The special object is colored black, and the valid location of the special object is used in objects linked lists, and other elements whenever a null value is required. Preferably, the special object is colored black by coloring a bit pattern in a header of the special object to represent black.

Abstract: In a data processing system, device, and method and a program storage medium, provided are data storage devices that store data and a data processing device that receives a list describing information about data stored in the data storage devices from the data storage devices and that receives and processes data selected based on the received list. Accordingly, a large amount of data can be processed with the data processing device irrespective of storage capacity of storage means.

Abstract: An apparatus has host ports for coupling hosts to data storage devices. The data storage devices are configured into logical storage units, and the apparatus is programmed with a mapping of the hosts to respective logical storage units. The apparatus decodes a host identifier and a logical storage unit specification from each data access request received at each host port, and determines whether or not the decoded host identifier and logical storage unit specification are in conformance with the mapping in order to permit or deny data access of the logical storage unit through the host port. For example, the apparatus includes a switch for routing the data storage access requests from the host ports to ports that provide access to the data storage, and a set of logical volumes of storage are accessible from each of the ports that provide access to the data storage.

Abstract: The present invention provides a control method for a storage device controller system provided with a first storage device controller that is connected to first and second storage devices storing data in the CKD format and the FBA format, respectively, and that has first and second communications control means that receive data input/output requests from a mainframe computer and an open system computer, respectively, and a second storage device that is connected to a third storage device storing data in the CKD format and that has third communications means connected to the second communications means, wherein the first storage device controller transmits a command to the second storage device controller if a data read request received from the open system computer is for data stored on the third storage device, and transmits the data that are read out from the third storage device by the second storage device controller to the open system computer.

Abstract: A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

Abstract: The present invention aims to embody a cache server which can provide the service of the same quality as a media server. A client sends a delivery request for a streaming delivery of a specific media file to a media server, and a cache checking unit of the cache server checks if the requested media file is stored in a cache file storing unit as a cache file. If it is stored, a file streaming delivering unit performs the streaming delivery to the client using the cache file. If not stored, the cache checking unit transfers the delivery request to the media server, and the media server performs the streaming delivery, and in parallel with the streaming delivery, at the cache server, a media file obtaining unit obtains the requested media file from the media server and stores the requested media file in the cache file storing unit.

Abstract: A memory device (10) includes an array (12) of memory cells arranged in rows and columns. Preferably, each memory cell includes a pass transistor coupled to a storage capacitor. A row decoder is coupled to rows of memory cells while a column decoder (14) is coupled to columns of the memory cells. The column decoder (14) includes an enable input. A variable delay (32) has an output coupled to the enable input of the column decoder (14). The variable delay (32) receives an indication (R/W?) of whether a current cycle is a read cycle or a write cycle. In the preferred embodiment, a signal provided at the output of the variable delay (32) is delayed if the current cycle is a read cycle compared to if the current cycle is a write cycle.

Abstract: A data processing system 2 is described including a cache memory 8 and a plurality of DRAM banks 16, 18, 20, 22. A victim select circuit 32 within a cache controller 10 selects victim cache storage lines 28 upon a cache miss such that unlocked cache storage lines are selected in preference to locked cache storage lines, non-dirty cache storage lines are selected in preference to dirty cache storage lines, and cache storage lines requiring a write back to a non-busy DRAM bank are selected in preference to cached storage lines requiring a write back to a busy DRAM storage bank. A DRAM controller 24 is provided that continuously performs a background processing operation whereby dirty cache storage lines 28 within a cache memory 8 are written back to their respective DRAM banks 16, 18, 20, 22 when these are not busy performing other operations and when the cache storage line has a least recently used value below a certain threshold.