Abstract: An image reading apparatus includes: a reading unit; a memory interface unit; a permission information obtaining unit; a permission determining unit; and a data recording unit. The reading unit reads an image. An external memory is removably connected to the memory interface unit and stores permission information. The permission information obtaining unit is configured to obtain the permission information from the external memory. The permission determining unit is configured to determine whether the obtained permission information is valid. The data recording unit is configured to record data corresponding to the image on the external memory connected to the memory interface unit if the obtained permission information is valid.

Abstract: A cache-memory control apparatus controls a level-1 (L1) cache and a level-2 (L2) cache having a cache line divided into a plurality of sub-lines for storing data from the L1 cache. The cache-memory control apparatus includes a control-flag adding unit, an L1 cache control unit, and an L2 cache control unit. The control-flag adding unit provides an SP flag to each of the sub-lines. The L1-cache control unit acquires an access virtual address, and, when there is no data at the access virtual address, outputs an L2 cache-access address to the L2-cache control unit. The L2-cache control unit switches the SP flag based on a virtual page number in an L1 index and a physical page number in an L2 index. Based on the SP flag, corresponding one of the sub-lines is written back to the L1 cache.

Abstract: A system for authenticating a memory card including: a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card; a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device; and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card.

Abstract: Data hologram recycling systems, methods and computer program products are configured to arrange data for storage in the intermediate data storage as data segments which are replicas of holographic storage segments for destaging to the holographic data storage, and to determine retrieval for recycling of the destaged holographic storage segments to which aggregated requests for deletion are directed. The retrieval determination may be based on a plurality of policies.

Abstract: Provided are a method, system and program for selecting storage clusters to use to access storage. Input/Output (I/O) requests are transferred to a first storage cluster over a network to access storage. The storage may be additionally accessed via a second storage cluster over the network and both the first and second storage clusters are capable of accessing the storage. An unavailability of a first storage cluster is detected when the second storage cluster is available. A request is transmitted to hosts over the network to use the second storage cluster to access the storage. Hosts receiving the transmitted request send I/O requests to the storage via the second storage cluster if the second storage cluster is available.

Abstract: A shared memory controller is provided for controlling access to a shared memory by a plurality of processors. At least one device includes a storage area for storing a respective address range for each of a plurality of memory regions. The at least one device further includes a permission table containing, for each of the plurality of memory regions, read and write permission data for each of the plurality of processors. A memory fault detector is coupled to the at least one device and has an input for receiving a memory access request including a memory address, a processor identification and a read/write indicator. The memory fault detector includes logic for determining whether a memory access according to the memory access request would conflict with the read and write permission data in the permission table.

Abstract: A method of obtaining data, comprising at least one sector, for use by at least a first thread wherein each processor cycle is allocated to at least one thread, includes the steps of: requesting data for at least a first thread; upon receipt of at least a first sector of the data, determining whether the at least first sector is aligned with the at least first thread, wherein a given sector is aligned with a given thread when a processor cycle in which the given sector will be written is allocated to the given thread; responsive to a determination that the at least first sector is aligned with the at least first thread, bypassing the at least first sector, wherein bypassing a sector comprises reading the sector while it is being written; and responsive to a determination that the at least first sector is not aligned with the at least first thread, delaying the writing of the at least first sector until the occurrence of a processor cycle allocated to the at least first thread by retaining the at least first s

Abstract: A system for authenticating a memory card including a capacity switching-type memory card host device including a capacity switch notification module which notifies a memory card targeted for exchanging information that the capacity switching-type memory card host device handles a capacity switching-type memory card, and a capacity switch authentication module which authenticates whether the targeted memory card is the capacity switching-type memory card, a capacity switching-type memory card including a capacity switching-type controller which flags the large-capacity expression register use flag on receipt of notification of being the capacity switching-type memory card host device, and a bus which transmits and receives data between the capacity switching-type memory card host device and the capacity switching-type memory card.

Abstract: A semiconductor device according to the present invention comprises a first non-volatile memory, a second non-volatile memory in which initial data is stored, and an initialization controller for initializing the first non-volatile memory, wherein the second non-volatile memory has anti-stress properties higher than those of the first non-volatile memory, and the initialization controller reads the initial data from the second non-volatile memory when the first non-volatile memory is initialized and copies the read initial data in the first non-volatile memory to thereby initialize the first non-volatile memory.

Abstract: A memory processing approach involves implementation of memory status-driven access. According to an example embodiment, addresses received at an address buffer are processed for access to a memory relative to an active location in the memory. Addresses corresponding to an active location in the memory array are processed prior to addresses that do not correspond to an active location. Data is read from the memory to a read buffer and ordered in a manner commensurate with the order of received addresses at the address buffer (e.g., thus facilitating access to the memory in an order different from that received at the address buffer while maintaining the order from the read buffer).

Abstract: A system for controlling the pacing of host data writes in response to changing system conditions allows for the use of variably controlled delays that facilitate asynchronous replication with bounded lag and smooth steady-state performance. Adding delay to the writes slows down the host and dampens activity spikes. A first storage device receives a write request, transmits data to a second storage device, and acknowledges the write request. An amount of additional write response time is controlled between when the write request is received and when the write request is acknowledged by the first storage device, where the amount of additional write response time is controlled according to system parameters including an amount of lag time between when the write request is received and when the write request is committed at the second storage device.

Abstract: The invention provides a smart card chip having a nonvolatile system memory (ROM, flash1), a Java Card Virtual Machine implemented in the nonvolatile system memory (ROM, flash1), a nonvolatile application memory (EEPROM, flash2), a volatile working memory (RAM) and a variables memory area reserved for global variables, wherein the variables memory area is reserved in the volatile working memory (RAM). The variables memory area is preferably reserved statically. The use of the variables can be limited to system packages and optionally additionally to preloaded (ROM/EEPROM) packages.

Abstract: Provided are a method, system, and article of manufacture for adjusting parameters used to prefetch data from storage into cache. Data units are added from a storage to a cache, wherein requested data from the storage is returned from the cache. A degree of prefetch is processed indicating a number of data units to prefetch into the cache. A trigger distance is processed indicating a prefetched trigger data unit in the cache. The number of data units indicated by the degree of prefetch is prefetched in response to processing the trigger data unit. The degree of prefetch and the trigger distance are adjusted based on a rate at which data units are accessed from the cache.

Abstract: A data storage device has a data storage medium configured to store a first version of data in parent sectors. The data storage device is configured to store a second version of the data in child sectors. The child sectors have the same logical block addresses as the parent sectors. A host operating system can read data from or write data to the child sectors by sending logical block addresses and a sector set number to the data storage device. The logical block addresses and the sector set number identify the child sectors. In response to receiving a request to access the child sectors, the data storage firmware identifies physical addresses that correspond to the logical block addresses and the sector set number. The data storage device uses the physical addresses to identify the location of the child sectors.

Abstract: Data for storage by holographic data storage is arranged in an intermediate data storage as data segments which are replicas of holographic storage segments. Files of data are aggregated into the data segments, and a destaging control determines the destaging of the data segments to the holographic data storage in accordance with a plurality of policies, such as whether a segment is full, a time threshold has been reached, or whether a threshold number of segments are “open”. The intermediate data storage may be arranged into a number of partitions at least equal to the number of sources having input to the data destaging system, the partitions comprising integral multiples of the data segments.

Abstract: A method for operating a computer data storage system stores snapshots of an active file system of the storage system at a plurality of destinations. A latest snapshot stored at each destination of the plurality of destinations is identified. Those data blocks which are newer than the latest snapshot stored at the each destination are sent to the each destination. The active file system is scanned to find each data block newer than the oldest snapshot stored at a selected destination, and all such data blocks are tagged. Those data blocks which are tagged are sent to the selected destination.

Abstract: A method for managing a cluster of file servers is disclosed. The method has the first step of writing coordinating information for a plurality of servers of the cluster of servers to a master mailbox record, the master mailbox record written to a specific location on each disk of a set of lock disks, the set of lock disks having a plurality of disks, the plurality of disks chosen so that in the event of failure of a server of the plurality of servers, at least one lock disk will be available to the remaining servers. The method has the second step of writing a second copy of eth coordinating information to the master mailbox record of the set of lock disks.

Abstract: A method may include counting the number of times each of a plurality of entries in a content addressable memory (CAM) matches one or more searches; grouping entries in the CAM into a first subset and a second subset based on the number of times each of the plurality of entries in the CAM matches one or more searches; and searching the first subset for a matching entry and, if no matching entry is found, searching the second subset for the matching entry.

Abstract: Various technologies and techniques are disclosed that improve implementation of concurrency control modes in a transactional memory system. A transactional memory word is provided for each piece of data. The transactional memory word includes a version number, a reader indicator, and an exclusive writer indicator. The transactional memory word is analyzed to determine if the particular concurrency control mode is proper. Using the transactional memory word to help with concurrency control allows multiple combinations of operations to be performed against the same memory location simultaneously and/or from different transactions. For example, a pessimistic read operation and an optimistic read operation can be performed against the same memory location.

Abstract: An apparatus is disclosed in which a storage controller cooperable with a host and a plurality of controlled storage is provided to localize an impact of a failure to a target disk in an affected segment. The storage controller includes a host write component to write a data object to a source image storage; a first copy component responsive to a first metadata state to control copying of the data object to a first target storage; a second copy component responsive to a second metadata state to perform either: copying the data object to a second target or causing the first copy component to copy the second target to the first target; and a third copy component to control cascaded copying of the data object to a third target storage. Either the second or the third copy component controls cascaded copying of a delimited data image subsequence responsive to a metadata state indicating currency of a data grain in either the second or the third target.