Abstract: Techniques for use in CDMA-based products and services, including replacing cache memory allocation so as to maximize residency of a plurality of set ways following a tag-miss allocation. Herein, steps forming a first-in, first-out (FIFO) replacement listing of victim ways for the cache memory, wherein the depth of the FIFO replacement listing approximately equals the number of ways in the cache set. The method and system place a victim way on the FIFO replacement listing only in the event that a tag-miss results in a tag-miss allocation, the victim way is placed at the tail of the FIFO replacement listing after any previously selected victim way. Use of a victim way on the FIFO replacement listing is prevented in the event of an incomplete prior allocation of the victim way by, for example, stalling a reuse request until such initial allocation of the victim way completes or replaying a reuse request until such initial allocation of the victim way completes.

Abstract: In one embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory and control logic coupled to the memory. The memory is configured to store translation data corresponding to one or more I/O translation tables stored in a memory system of a computer system that includes the IOMMU. The control logic is configured to translate an I/O device-generated memory request using the translation data. The translation data includes a type field indicating one or more attributes of the translation, and the control logic is configured to control the translation responsive to the type field.

Abstract: A storage controller, cooperable with host computer apparatus, and a plurality of controlled storage apparatus, comprises a host write component operable to write a data object to a source data image at one of the plurality of controlled storage apparatus; a first copy component responsive to a first metadata state and operable to control copying of the data object to a first target data image at one of the plurality of controlled storage apparatus; a second copy component responsive to a second metadata state and operable to perform one of: controlling copying of the data object to a second target data image at one of the plurality of controlled storage apparatus; and causing the first copy component to perform copying of the second target data image to the first target data image.

Abstract: Host system data files are written directly to a large erase block flash memory system with a unique identification of each file and offsets of data within the file but without the use of any intermediate logical addresses or a virtual address space for the memory. Directory information of where the files are stored in the memory is maintained within the memory system by its controller, rather than by the host. Each data file is uniquely identified in a file directory, which points to entries in a file index table (FIT) of data groups that make up the file and their physical storage locations in the memory.

Abstract: A storage apparatus is provided with a storage area for storing data sent from a host computer, and a virtual/logical volume to which a dynamically variable storage area is allocated from within the storage area, the volume being provided to the host computer, and this storage apparatus is configured to include: a pool area generation unit for generating a plurality of pool areas composed from the storage area; a setting unit for setting, for each of the plurality of pool areas generated by the pool area generation unit, an allocation unit size for allocating a storage area from within the storage area provided by the pool area to the virtual/logical volume; a selecting unit for selecting, when data to be stored in the storage area is sent from the host computer, a pool area from among the plurality of pool areas having the allocation unit size set by the setting unit, in accordance with the size of the sent data; and an allocation unit for allocating a storage area from within the storage area provided by th

Abstract: Data for storage by holographic data storage is arranged in an intermediate data storage as data segments which are replicas of holographic storage segments. Files of data are aggregated into the data segments, and a destaging control determines the destaging of the data segments to the holographic data storage in accordance with a plurality of policies, such as whether a segment is full, a time threshold has been reached, or whether a threshold number of segments are “open”. The intermediate data storage may be arranged into a number of partitions at least equal to the number of sources having input to the data destaging system, the partitions comprising integral multiples of the data segments.

Abstract: In a multi-port register file of a storage unit within a processor, an improved bitcell design for storing a data bit is disclosed. The bitcell comprises a first set of read bitlines having a first load and a second set of read bitlines having a second load, in which the second load is substantially equal to the first load. The bitcell also comprises a signal driving circuit having a first node and a second node. The first node is connected to the first set of read bitlines and the second node is connected to the second set of read bitlines.

Abstract: A recording device which records data onto a recording medium includes a nonvolatile memory storing and holding data on a free capacity of the recording medium, and a control unit controlling the data recording. The control unit determines the free-capacity data stored in the nonvolatile memory based on the total capacity of the recording medium when power is turned on. When the determination result indicates that a value of the free-capacity data stored in the nonvolatile memory does not exceed a value of the total capacity of the recording medium, the control unit records the data onto the recording medium with reference to the free-capacity data. When the power is turned off, the control unit updates the free-capacity data so as to reduce the value of the free-capacity data by as much as an amount of the data recorded onto the recording medium.

Abstract: In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to translate an I/O device-generated memory request using the translation data. The translation data corresponds to one or more device table entries in a device table stored in a memory system of a computer system that includes the IOMMU, wherein the device table entry for a given request is selected by an identifier corresponding to the I/O device that generates the request. The translation data further corresponds to one or more I/O page tables, wherein the selected device table entry for the given request includes a pointer to a set of I/O page tables to be used to translate the given request.

Abstract: A system for a host-based RAID solution in a shared storage environment is provided in which the compute blades of a system are coupled to one or multiple concentrators. The concentrators serve as a switch or expander to couple each of the compute blades to a shared storage resource. Within the shared storage resource, a set of drives is configured in a RAID array. The shared disk drives are partitioned so that each partition is dedicated to one of the compute blades of the system. Multiple sets of drives may be used so that the collective set of drives can be configured as part of a RAID volume that includes mirroring between at least two of the drives of the RAID volume, such as RAID 1 or RAID 0+1, in which each set of drives is a mirror of the other set of drives and the content associated with each of the compute blades is striped across multiple drives in each of the two sets of drives.

Abstract: A method of apparatus to free at least a portion of memory space of a memory device from at least a portion of a stored data block, wherein the freeing is based on the block sequence number of the stored data block and/or a quality indicator value related to at least a portion of the stored data block. Other embodiments may be described and claimed.

Abstract: Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.

Abstract: Systems and methods for program directed memory access patterns including a memory system with a memory, a memory controller and a virtual memory management system. The memory includes a plurality of memory devices organized into one or more physical groups accessible via associated busses for transferring data and control information. The memory controller receives and responds to memory access requests that contain application access information to control access pattern and data organization within the memory. Responding to memory access request includes accessing one or more memory devices. The virtual memory management system includes: a plurality of page table entries for mapping virtual memory addresses to real addresses in the memory; a hint state responsive to application access information for indicating how real memory for associated pages is to be physically organized within the memory; and a means for conveying the hint state to the memory controller.

Abstract: Methods and apparatus to provide improved input/output (I/O) address translation lookaside buffer performance are described. In one embodiment, one or more entries of a cache (e.g., an I/O address translation lookaside buffer) are locked in response to a request to lock the one or more entries. Other embodiments are also described.

Abstract: Devices, systems and methods of reduced-power memory address generation. For example, an apparatus includes: a carry save adder including at least a first set of adders and a second set of adders, wherein the adders of the first set are able to receive a first number of input bits and to produce a first number of outputs, and wherein adders of the second set are able to receive a second number of input bits and to produce the first number of outputs.

Abstract: A “virtual on-chip memory” that provides advantages as compared to an on-chip memory that utilizes a cache. In accordance with the invention, when a CPU attempts to access a memory address that is not on-chip, the access is aborted and the abort is handled at a page level. A single page table is utilized in which each entry constitutes an address in the virtual address space that will be mapped to a page of on-chip memory. The CPU obtains the missing data, updates the page table, and continues execution from the aborted point. Because aborts are handled at the page level rather than the line level, the virtual on-chip memory is less expensive to implement than a cache. Furthermore, critical real-time applications can be stored within a non-virtual portion of the memory space to ensure that they are not stalled.

Abstract: One embodiment of the invention relates to the transfer of content between a host computer that issues OAS access requests and a block I/O storage system. Specifically, a host computer may issue an access request for a content unit that identifies the content unit is an object identifier. The request may be received by a second server, which may determine the block address(es) on the block I/O storage system at which the content unit is stored. A request may then be sent to the block I/O storage system to retrieve the content stored at the requested block address(es) and the block I/O storage system may return the content.

Abstract: An apparatus, program product and method stripe value data associated with each of a plurality of keyed data sets across a plurality of processes in a data process set and accessing a first keyed data set among the plurality of keyed data sets using at least one of the plurality of processes. Value data is striped by dividing a keyed data set among the plurality of keyed data sets across the plurality of processes in the data process set based on a striping strategy.

Abstract: A memory system for providing a slow command decode over an untrained high-speed interface. The memory system includes a memory system having a memory interface device, an untrained high-speed interface, and a memory controller. The untrained high-speed interface is in communication with the memory interface device. The memory controller generates slow commands and transmits the slow commands to the memory interface device via the untrained high-speed interface. The slow commands operate at a first data rate that is slower than a second data rate utilized by the high-speed interface after it has been trained. The memory interface device receives the slow commands via the untrained high-speed interface, decodes the slow commands, and executes the slow commands.

Abstract: An apparatus and method for managing a memory of a computer and controlling a booting operation of the computer, are provided. The computer includes a memory having a user area and a protected security area (PSA). The user area has a management area. The method includes assigning a first partition to the user area of the memory; storing first partition information in the management area of the user area, the first partition information pertaining to the first partition; assigning a second partition to the PSA in response to an access signal, the access signal authorizing access to the PSA; storing, in the management area, second partition information pertaining to the second partition; storing the second partition information in the PSA; and removing the second partition information from the management area after storing the second partition information in the PSA.

Abstract: A clasp for a pair of wristbands on a digital watch having a pager with a radio frequency receiver such that the wristbands comprise an antenna that has its circuit completed and closed into a loop antenna when a user snaps the wristbands together with the clasp. The clasp has a catch shaft welded or soldered to a clasp body such that electrical contact between the antenna in the wristbands is thereby improved.