Abstract: Systems and methods are provided for A computer-implemented method for simulating behavior of an electrical circuit across a range of frequencies from 0 to fmax. A base function is determined that outputs magnitudes across the range of frequencies. A correction function is determined that outputs magnitudes across the range of frequencies. The base function is combined with the correction function to generate a circuit behavior model that provides magnitudes across the range of frequencies. Behavior of the electrical circuit is simulated using the circuit behavior model.

Abstract: A method of fabricating a semiconductor device may include designing a layout including first and second gate patterns, first and second dummy gate patterns, and third and fourth gate patterns sequentially arranged in a first direction; forming first to fourth sacrificial patterns and first and second dummy sacrificial patterns, which correspond to the first to fourth gate patterns and the first and second dummy gate patterns respectively, on a substrate using a photomask manufactured based on the layout; and performing an optical proximity correction on the layout. The optical proximity correction may include measuring distances between adjacent ones of the sacrificial and dummy sacrificial patterns in the first direction to provide measured distances, comparing a mean value of the measured distances with a mean value of target distances to obtain a first distance therebetween, and reducing a distance between the first and second dummy gate patterns by the first distance.

Abstract: A method of adding another circuit component with operations executable on an FPGA to an FPGA configuration, wherein the FPGA configuration already has at least one existing circuit component with operations executable on the FPGA, which is locally distributed in the FPGA configuration, includes synthesizing the further circuit component to obtain a further netlist, and distributed arranging of the further netlist taking into account the at least one existing circuit component in the FPGA configuration.

Abstract: A method for non-invasive characterisation of a cell for a battery is provided, the method comprising: measuring a magnetic field generated by the cell using a plurality of magnetic field sensors positioned adjacent to the cell, the measuring producing magnetic field sensor data, wherein the measuring is performed while the cell is in a passive state; determining current density profile data across the cell based on the magnetic field sensor data; and determining a condition of the cell using the current density profile data.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, an electronic design and applying one or more predefined rules to the electronic design. Embodiments may further include automatically generating a connectivity aware system signal flow diagram and causing a display of the connectivity aware system signal flow diagram at a graphical user interface.

Abstract: Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Abstract: A filter manufacturing method and a filter manufactured by the filter manufacturing method are disclosed. The filter manufacturing method includes designating a use mode in a resonator to a first resonance mode, in response to designating to the first resonance mode, setting a band selected from a designated first frequency band to a passband in the resonator, switching the use mode in the resonator from the first resonance mode to a second resonator mode, in response to switching to the second resonance mode, setting a band selected from the first frequency band except for the passband to a stopband in the resonator, and manufacturing a primary filter including the resonator to which the passband and the stopband are set.

Abstract: In some embodiments, a computer-implemented method for designing an integrated circuit using transistor placement optimization is provided. A computing system receives a specification for the integrated circuit. The specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors. The computing system determines an initial location and an orientation on a canvas for each transistor in the plurality of transistors. The computing system uses an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors. The computing system uses a local refinement technique to optimize the rough placement to generate a fine placement, and uses a routing technique to generate a routing for the fine placement to generate a completed design.

Abstract: The memory device includes a die with a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of planes is oriented such that its major dimension extends in a second direction that is different than the first direction such that the non-common peripheral circuitry area of each plane is immediately adjacent the at least one common peripheral circuitry area in the CMOS layer.

Abstract: A neuromorphic system according to an embodiment of the invention includes an input signal section that generates an input signal, a synapse section that includes a plurality of synaptic units that receive the input signal and makes a current to flow according to a set weight, each of the plurality of synaptic units including a plurality of non-volatile memory cells capable of selectively storing a logical state, the non-volatile memory cells being arranged in a memory array that include input electrode lines and output electrode lines crossing each other, and generates an output signal for each output electrode line by the input signal, a digital calculation section that digitizes the output signal generated for each output electrode line and calculates a sum of the digitized output signals, and a controller section that controls the input signal section, the synapse section, and the digital calculation section, and the controller section designates the number of digitized digits for each output electrode li

Abstract: Systems and methods for operating quantum systems are described. A controller of a quantum system can generate a command signal. The quantum system can include quantum hardware having a plurality of qubits. An interface of the quantum system can control the quantum hardware based on the command signal to sample an input vector represented by the first set of qubits, where the input vector includes mixed states with different Hamming weights. The interface can control the quantum hardware to entangle the first set of qubits to the second set of qubits, where the second set of qubits represent a count of nonzero elements in the input vector. The interface can control the quantum hardware to generate an output vector based on the entanglement of the first set of qubits to the second set of qubits, where the output vector includes one or more states having a specific Hamming weight.

Abstract: According to one embodiment, a data analyzing apparatus acquires data containing the number N of analysis target samples (where N is an integer larger than or equal to 2). The apparatus performs a matrix factorization upon the data to factorize the data into the number K of basis samples and the number K of weights corresponding to the number K of basis samples (where K is an integer larger than or equal to 2), and fixes part of the K basis samples to specific basis samples in the matrix factorization.

Abstract: An integrated circuit includes a first region of the integrated circuit including a first set of pins extending in a first direction, being on a first level, and having a first width in a second direction different from the first direction. The first region has a first height in the second direction. An integrated circuit further includes a second region of the integrated circuit adjacent to the first region, the second region including a second set of pins extending in the first direction, being on a first level, being separated from the first set of pins in the second direction, and having a second width in the second direction, the first width being different from the second width. The second region has a second height in the second direction different from the first height, and the first level is a first metal layer of the integrated circuit.

Abstract: Globally placing a circuit design includes adjusting indicated capacity levels for placement bins associated with a target integrated circuit, based on first levels of demand for resources by instances in the circuit design in regions of the target IC. Region constraints restrict placement of the instances in the regions, and the regions include two or more two or more overlapping regions. Tracked levels of demand for resources in the placement bins are adjusted, after adjusting the indicated capacity levels, based on the indicated capacity levels, a target utilization level of the resources in the placement bins, and a current placement. The current placement of the instances is updated based on a density gradient of an electrostatics-based model of the tracked levels of demand, and repeating adjusting the tracked levels of demand and updating the current placement are repeated in response to the density gradient failing to satisfy a threshold.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: Described herein are techniques for routing conductive wires in a wireless power transfer pad. Such techniques may comprise routing, for a length of wiring between a power source and an inductive coil, a first conductive wire configured to carry a first current, routing, for a first portion of the length of wiring, a second conductive wire next to the first conductive wire, wherein the second conductive wire is configured to carry a second current having a direction that is substantially opposite that of the first current, and routing, for a second portion of the length of wiring, a portion of the inductive coil next to the first conductive wire, wherein the portion of the inductive coil is configured to carry a third current having a direction that is substantially opposite that of the first current.

Abstract: A method, system, and computer program product are disclosed for implementing enhanced noise impact on function (NIOF) analysis of an IC design having nets in multiple different variable voltage domains next to each other and modeling all multiple worst-case victim-aggressor voltage configurations in a single run leveraging noise abstracts characterized at a single voltage corner. The NIOF analysis enables accurately identifying incorrect victim switching or functional fails, effectively and efficiently providing design verification and the ability to sign-off an IC design with a single run, and enable modifying an integrated circuit design to fix NIOF failures, and fabricating an integrated circuit.

Abstract: Method provides accurate state-of-health (SOH) diagnostics and prognostics during the whole-life-service of a lithium-ion battery by considering the effects of state-of-charge (SOC) and SOH on certain parameters (such as consideration of nonlinearity of the terminal voltage) during the process of SOC diagnostics and prognostics. The method integrates Lebesgue sampling and equivalent circuit model (ECM) analysis, which greatly decreases computation cost and uncertainty accumulation to provide efficient acquisition of open circuit voltage (OCV) determinations for the ECM process. The OCV curve of the battery was obtained during Hybrid Pulse Power Characterization testing by fitting a series of selected OCV points after enough rest of the subject battery. Identified parameters of ECM are updated according to terminal voltage measurement to enable accurate SOC estimation and prediction during the period from full charge to full discharge of the battery.

Abstract: A routing assembly for an electronic device has a plurality of connectors ports and each of the connector ports contains a first connector connected to one or more cables. Cables are directly terminated, at first ends thereof, to terminals of the first connectors and the cables can be embedded in a routing substrate. The routing substrate has an opening which accommodates a chip package. Second ends of the cables are terminated to second connectors arranged in the package opening and the second connectors are in turn connected to the chip package.

Abstract: A method includes acquiring a design layout of a standard cell, extracting feature information of one or more vias in the standard cell from the design layout, performing a circuit simulation to obtain first simulation outputs of the standard cell for input patterns by applying a first abnormal resistance value as a parasitic resistance value of a first via among the one or more vias, the first abnormal resistance value being different from a nominal parasitic resistance value of the first via, determining whether the first simulation outputs match corresponding expected outputs of the standard cell for the input patterns, and in response to one or more simulation outputs among the first simulation outputs not matching the corresponding expected outputs, recording one or more defect types for the first via having the first abnormal resistance value along with corresponding input patterns and corresponding simulation outputs.