Patents Examined by Jack Chiang
  • Patent number: 11415896
    Abstract: In a dissection method for layout patterns in a semiconductor device, a design layout is divided into a plurality of patches. A plurality of first dissection points for target layout patterns in the target patch and neighboring layout patterns in the neighboring patches are set based on vertexes of the target and neighboring layout patterns. At least one second dissection point for at least one exceptional layout pattern is set. The at least one exceptional layout pattern is a layout pattern in which the first dissection points are not set and which extends to pass through boundaries of one patch. A plurality of third dissection points for the target layout patterns and the neighboring layout patterns are set based on the first and second dissection points. The target layout patterns are divided into a plurality of target segments based on the first, second and third dissection points.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 16, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Wook Kim
  • Patent number: 11409939
    Abstract: Example test generation systems and methods are described. In one implementation, a hardware test suite generator includes a script reader that receives a test definition script and parses the test definition script. A test generator receives the parsed test definition script from the script reader and creates a test suite. A template reader receives a test definition template and parses the test definition template. A code generator receives the parsed test definition script from the script reader and receives the parsed test definition template from the template reader.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: August 9, 2022
    Assignee: VAXEL Inc.
    Inventor: Jun Takara
  • Patent number: 11409936
    Abstract: A standard cell establishment method is disclosed. The standard cell establishment method includes the following operations: setting a first implant split case; obtaining a plurality of characteristic parameters according to the first implant split case; applying the plurality of characteristic parameters to a device delay metric so as to obtain a speed parameter; optimizing a channel parameter if the speed parameter is better than a previous speed parameter; and establishing a standard cell if the channel parameter is optimized successfully.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: August 9, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jei-Cheng Huang, Tsung-Yu Tsai
  • Patent number: 11403452
    Abstract: Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (YLV), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. The plurality of circuit blocks may include circuit blocks having different design window sizes, and may be configured to support different phases of a yield learning ramp up process. The YLV may further include a yield learning controller configured to control circuit block testing, and bypasses configured to partially or fully replicate the behavior of improperly functioning or untested circuit blocks. Some embodiments may include techniques for software implementation of the YLV, such as by invoking a computer to receive data representative of a design of the YLV, and based on the data representative of the design of the integrated circuit, causing the computer to generate data representative of YLV.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: August 2, 2022
    Assignee: Synopsys, Inc.
    Inventor: Kee Sup Kim
  • Patent number: 11404889
    Abstract: A battery-disconnect circuit may include a latch, a battery-disconnect subcircuit, and a power-enable subcircuit. The battery-disconnect subcircuit may be configured to control current leakage. The battery-disconnect subcircuit may be connected to the latch. The latch may be configured to maintain a power supply state of the battery-disconnect subcircuit, a no-power supply state of the battery-disconnect subcircuit, or both. The power-enable subcircuit may be connected to the battery-disconnect subcircuit. The power-enable subcircuit may be configured to switch the battery-disconnect subcircuit to the power supply state based on an enable signal. The power-enable subcircuit may be configured to switch the battery-disconnect subcircuit to the no-power supply state based on an off signal.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: August 2, 2022
    Assignee: GoPro, Inc.
    Inventors: Casimir Karczewski, Aaron O'Brien, Rajesh Madhur, Sameer Mysore Venugopal
  • Patent number: 11396241
    Abstract: A series circuit includes a capacitor connected in series with output terminals of a power converter. The power converter provides an auxiliary voltage and a controller controls the auxiliary voltage according to a selected function, such that the series circuit behaves as a capacitor, an inductor, or an impedance, based on the selected function. The controller may sense a voltage across the capacitor and use the sensed voltage to control the auxiliary voltage according to the selected function. The series circuit may be connected in parallel with output terminals of an AC-DC converter, wherein the series circuit operates according to a selected mode to produce the auxiliary voltage, and the auxiliary voltage substantially cancels a low frequency AC voltage ripple across the capacitor, such that a substantially pure DC output voltage is delivered to the load.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: July 26, 2022
    Assignee: Queen's University at Kingston
    Inventor: Yan-Fei Liu
  • Patent number: 11379644
    Abstract: An IC chip test engine selects an instrument of an IC design based on an instrument access script, wherein the selected instrument comprises an IP block and a test data register (TDR) logically arranged upstream from the IP block. The IC chip test engine can also identify a set of SIBs gating access to the selected instrument and select a scan chain for operating the set of SIBs to control access to the selected instrument. The IC chip test engine augments the scan chain with data to cause at least a furthest downstream SIB of the set of SIBs that gates access to the selected instrument to transition to an opened state. The IC chip test engine can generate a set of load vectors for the scan chain to load the TDR of the selected instrument with data to apply a respective test pattern to the IP block.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: July 5, 2022
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Rajesh Khurana, Divyank Mittal, Sagar Kumar, Vivek Chickermane
  • Patent number: 11361138
    Abstract: Described is an apparatus for supporting Over-The-Air Hardware Updates comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to be fastened and electrically coupled in one or more regions to one or more respectively corresponding semiconductor dies. The second circuitry may be operable to configure the one or more regions of the first circuitry. The third circuitry may be operable to provide a set of wirelessly-received configuration instructions to the second circuitry.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 14, 2022
    Assignee: Shenzhen Chipuller Chip Technology Co., Ltd.
    Inventors: Hao Hua, Jawad Nasrullah
  • Patent number: 11360382
    Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: June 14, 2022
    Assignee: Synopsys, Inc.
    Inventors: Thomas Christopher Cecil, Kevin Hooker
  • Patent number: 11347925
    Abstract: A system and method for laying out power grid connections for standard cells are described. In various embodiments, a standard cell uses unidirectional tracks for each of the multiple power vertical metal 3 layer tracks and power horizontal metal 2 tracks. One or more of the multiple vertical metal 3 layer posts are routed with a minimum length based on a pitch of power horizontal metal 2 layer straps. One or more vertical metal 1 posts used for a power connection or a ground connection are routed from a top to a bottom of an active region permitting multiple locations to be used for connections to one of the multiple power horizontal metal 2 layer straps. Two or more power horizontal metal 2 layer straps are placed within a power metal 2 layer track without being connected to one another.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: May 31, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Richard T. Schultz
  • Patent number: 11342914
    Abstract: Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and/or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output pre-selected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: May 24, 2022
    Assignee: Juniper Networks, Inc.
    Inventor: Gustav Laub, III
  • Patent number: 11334703
    Abstract: Various examples of conductor features in integrated circuit layouts are disclosed herein. In an example, a method includes initializing a layout for fabricating an integrated circuit. A plurality of fill cells is inserted into the layout. The plurality of fill cells includes a plurality of fill line shapes that correspond to conductive lines of the integrated circuit. Thereafter, a design is inserted into the layout that includes a plurality of functional shapes. A conflicting subset of the plurality of fill line shapes of the plurality of fill cells that conflict with the plurality functional shapes are removed. The layout that includes the plurality of fill cells and the design is provided for fabricating the integrated circuit.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: May 17, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Cheng Yeh, Yen-Sen Wang, Ming-Yi Lin
  • Patent number: 11328873
    Abstract: A parallel plate capacitor structure in an integrated circuit has a first plate and a second plate separated by an insulator, such as a dielectric. Both plates are connected to an interconnect structure at a plurality of connection points. The area of the first plate that overlaps with the second plate is identified. This overlap region does not include any connection points on the first plate. For this overlap region, the lumped element model for the first plate includes nodes on the edge of the overlap region (edge nodes), and lumped resistances between the edge nodes and the node connected to the lumped capacitance. In one embodiment, the lumped element model also includes a common node, all of the edge nodes are connected to the common node by lumped resistances, and the common node is connected by a negative resistance to the lumped capacitance.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: May 10, 2022
    Assignee: Synopsys, Inc.
    Inventors: Ralph Benhart Iverson, Xuerong Ji
  • Patent number: 11314915
    Abstract: A method of designing a layout of a semiconductor device includes determining from among a plurality of integrated circuit (IC) blocks in the semiconductor device a selection IC block for which a layout is to be changed, changing an spacing interval at which fin structures included in the selection IC block are spaced apart from each other in a first direction from a first spacing interval to a second spacing interval, and determining in the selection IC block locations of source/drain regions connected to the fin structures spaced apart from each other in the first direction at the second spacing interval.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: April 26, 2022
    Inventors: Jin Kim, Byungmoo Kim, Jaehwan Kim, Junsu Jeon
  • Patent number: 11314912
    Abstract: An IC design data base generating method, including: receiving a condition parameter, which comprises a process parameter and an operating parameter range comprising at least one operating parameter; and testing at least one cell according to the process parameter and the operating parameter range to generate a delay value data base. The delay value data base comprises a plurality of delay values, wherein the plurality of delay values for an identical cell correspond to the operating parameter range with an identical type but different value. An IC design method using the delay value data base is also disclosed.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: April 26, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventors: Szu-Ying Huang, Mei-Li Yu, Yu-Lan Lo, Shu-Yi Kao
  • Patent number: 11308257
    Abstract: A structure including a plurality of dielectric regions is described. The structure can include a rivet cell. The rivet cell can include a set of stacked vias. The rivet cell can extend through a stress hotspot of the structure. A length of the rivet cell can thread through at least one dielectric region among the plurality of dielectric regions. The rivet cell can be among a number of rivet cells inserted in the stress hotspot. The stress hotspot can be among a plurality of stress hotspots across the structure. A length of the rivet cell can be based on a model of a relationship between the length of the rivet cell and an energy release rate of the structure. The rivet cell can thread through an interface between a first dielectric region and a second dielectric region having different dielectric constants.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: April 19, 2022
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, David Wolpert, Atsushi Ogino, Matthew T. Guzowski, Steven Paul Ostrander, Tuhin Sinha, Michael Stewart Gray
  • Patent number: 11301613
    Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: April 12, 2022
    Assignee: Coventor, Inc.
    Inventors: Qing Peng Wang, Shi-Hao Huang, Yu De Chen, Rui Bao, Joseph Ervin
  • Patent number: 11295054
    Abstract: A method for designing a power network is provided and includes: initializing via widths and power-trace widths; determining whether utilization rates of first, second and third routing tracks are respectively equal to first, second and third values; when said utilization rate of said first routing tracks is not equal to said first value, adjusting said distance between first and second power traces until said utilization rate thereof is equal to said first value; when said utilization rate of said second routing tracks is not equal to said second value, adjusting said distance between third and fourth power traces until said utilization rate thereof is equal to said second value; and when said utilization rate of said third routing tracks is not equal to said third value, adjusting said distance between fifth and sixth power traces until said utilization rate thereof is equal to said third value.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: April 5, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Long Wang, Jerming Lin, Yi Li, Xiaojing Li, Di Al
  • Patent number: 11295051
    Abstract: The present disclosure relates to system(s) and method(s) for interactively controlling the course of a functional simulation of DUV/SUV. The system comprises a testbench and the DUV/SUV connected to the testbench. The testbench generates a set of input data/packets as a stimulus to be processed by the DUV/SUV. The set of input data/packets is generated to simulate and verify the DUV/SUV. Further, the testbench identifies a pre-defined event at runtime during the simulation. Upon identification of the event, the testbench is configured to pause the simulation and transmit a notification message to a user indicating the occurrence of the event. Further, the testbench waits for a pre-defined time interval to receive one or more user inputs. The testbench further generates new stimulus based on the one or more user inputs and resumes the paused simulation with the new stimulus, thereby controlling the course of the functional simulation.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: April 5, 2022
    Assignee: HCL Technologies Limited
    Inventors: Manickam Muthiah, Jabeer Ahamed Mohammed Nowshath, Sathish Kumar Krishnamoorthy
  • Patent number: 11289919
    Abstract: The present disclosure discloses a charging control system, which includes: a master device, including a first USB interface and a first charging management circuit; at least one slave device, including a second USB interface and a second charging management circuit; a gating control circuit, which is arranged in the master device or the slave device, wherein an input terminal of the gating control circuit is coupled to the first USB interface and the second USB interface, and an output terminal of the gating control circuit is coupled to the first charging management circuit and the second charging management circuit to select and control a charging USB interface of the first charging management circuit and a charging USB interface of the second charging management circuit. Through the above mentioned way, multiple charging modes of the master device and the slave device may be implemented without software support.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: March 29, 2022
    Assignee: Huizhou TCL Mobile Communication Co., Ltd
    Inventors: Chulong Sheng, Wentao Huang