Abstract: A power feeding control device controls a power feeding system including a plurality of battery cells feeding power to a load, a bypass lines which connects or disconnects each of the battery cells and the load, an external power feeding unit which is connected in parallel with the load and feeds power to the load. Before the bypass line starts switching of a connection state between each of the battery cells and the load, supply voltage from the external power feeding unit to the load is increased. Further, after the bypass line switches the connection state between each of the battery cells and the load, the supply voltage from the external power feeding unit to the load is decreased.

Abstract: The present disclosure describes a method for optimizing metal cuts in standard cells. The method includes placing a standard cell in a layout area and inserting a metal cut along a metal interconnect of the standard cell at a location away from a boundary of the standard cell. The method further includes disconnecting, at the location, a metal portion of the metal interconnect from a remaining portion of the metal interconnect based on the metal cut.

Abstract: An approach is disclosed herein for test sequence processing that is applicable to machine learning model generated test sequences as disclosed herein. The test sequence processing includes classification, grouping, and filtering. The classification is generated based on the execution of the test sequences. The grouping is performed based on information captured during the classification of the test sequences. The filtering is performed on a group by group basis to remove redundant test sequences.

Abstract: A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.

Abstract: Methods for optimizing an aspect of a patterning process based on defects. For example, a method of source and mask optimization of a patterning process includes obtaining a location on a substrate having a threshold probability of having a defect; defining an defect ambit around the location to include a portion of a pattern on the substrate and one or more evaluation points associated with the portion of the pattern; determining a value of a first cost function based on a defect metric associated with the defect; determining a first guide function for the first cost function, wherein the first guide function is associated with a performance metric of the patterning process at the one or more evaluation locations within the defect ambit; and adjusting a source and/or a mask characteristic based on the value of the first cost function, and the first guide function.

Abstract: The present invention provides a method, medium, and system for determining demolition points of a large building, which falls within the technical field of building demolition and construction. The method for determining demolition points of a large building includes: establishing a three-dimensional model of a large building to be demolished; analyzing, based on the three-dimensional model of the large building to be demolished, a force condition of each point to form a three-dimensional force model; calculating, based on the three-dimensional force model of the large building to be demolished, to obtain a demolition point tree of the building; and marking each demolition point in a demolition point sequence in the three-dimensional model of the large building to be demolished. In the process of multi-point synchronous demolition of large buildings, the demolition points of large buildings can be located according to the automatic analysis of the demolition order.

Abstract: A method of operating a computing device for detecting clock domain crossing (CDC) violation in a design of a memory device, the method includes parsing a Netlist to generate a circuit database, parsing a clock tree using the circuit database to generate a clock tree database, extracting a non-toggled point using the clock tree database to generate a false path database based on the non-toggled point, and extracting a CDC violation identified from one or more simulation waveforms using the clock tree database and the false path database.

Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

Abstract: A method and a system for verifying an integrated circuit stack having a silicon photonic (SIPH) device is introduced. A single first dummy layer is added to at least one terminal of the SIPH device in a first layout of the first integrated circuit, wherein a shape of the single first dummy layer added to the at least one terminal of the SIPH device maps a shape of the at least one terminal of the SIPH device. A first layout versus schematic (LVS) check is performed on the first integrated circuit based on the single first dummy layer added to the at least one terminal of the SIPH device to verify a connection of the SIPH device in the first integrated circuit.

Abstract: An optimization method for a digital integrated circuit is provided. Under the precondition of satisfying certain timing constraints, circuit-level, path-level and gate cell-level features of a circuit are extracted to construct a leakage power optimization model, and optimization data from commercial circuit optimization tools is used to train the model to predict voltage threshold types of gate cells after circuit optimization, such that the circuit can be optimized by adjusting voltage thresholds of gate cells in a post-routing gate-level netlist, thus realizing the optimization objective of reducing leakage power.

Abstract: The present disclosure describes an example method for routing a standard cell with multiple pins. The method can include modifying a dimension of a pin of the standard cell, where the pin is spaced at an increased distance from a boundary of the standard cell than an original position of the pin. The method also includes routing an interconnect from the pin to a via placed on a pin track located between the pin and the boundary and inserting a keep out area between the interconnect and a pin from an adjacent standard cell. The method further includes verifying that the keep out area separates the interconnect from the pin from the adjacent standard cell by at least a predetermined distance.

Abstract: Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.

Abstract: A method of manufacturing a semiconductor device includes: generating a design data of the semiconductor device; and generating a design layout according to the design data. The design layout includes: a first power rail; a second power rail; a first cell including a first first-type active region and a first second-type active region, wherein a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail; a second cell having a second first-type active region and a second second-type active region; and a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.

Abstract: An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

Abstract: Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs.

Abstract: A method and apparatus for identifying net text in a net list at each hierarchical level of the net list is disclosed. The identified net text is then associated with the hierarchical level in which the net text was found. Each cell in the net list can then be optimized by exploding the net list of at least one cell. Once exploded, the identified net text together with the associated hierarchical level of each progeny cell of each exploded cell is associated with the net list of the exploded cell.

Abstract: A method to place repeaters on existing structured routes based on user specified locations. Location can be specified in multiple ways. For example, a set of fixed repeating distances (starting from a driver), number of repeaters (spread evenly on net routing), an absolute cutline dissecting the existing nets routing (e.g., x or y coordinate measure from the origin of the cell), relative cutline dissecting the existing nets routing (e.g., x or y coordinate measured from the origin of the nets bounding box), etc. can specify location. A repeater legalization procedure allows a user to arrange repeaters in various forms thus legalizing them to meet specific design requirements. A preview mode is provided where results are presented in the form of annotations (e.g., cartoon drawings) displayed on a canvas (e.g., display screen) rather than in the form of real layout objects in a database.

Abstract: Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).

Abstract: Systems, computer-implemented methods and/or computer program products are provided to facilitate operation of a quantum circuit on a set of qubits via providing and implementing decompositions of one or more unitary matrices. According to an embodiment, a system can implement a unitary matrix by providing and implementing a decomposition of the unitary matrix, to thereby facilitate operation of and/or operate a quantum circuit on a set of qubits. The system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a unitary matrix management component that decomposes a defined 4×4 unitary matrix into a defined circuit comprising a sequence of universal gates. The sequence of universal gates can be a same sequence for each defined 4×4 unitary matrix of a set of candidate 4×4 unitary matrices including the defined 4×4 unitary matrix.

Abstract: Methods and systems for performing fault injection testing on an integrated circuit hardware design.