Abstract: The present disclosure provides a photomask and a method of forming a photomask, in which the photomask may obtain an optimized uniformity via a simplified process flow. The photomask includes a plurality of stair-like patterns parallel disposed with each other, wherein each of the stair-like patterns includes a plurality of first right angles at one side and a plurality of second right angle at another side opposite to the side, and each of the first right angles and each of the second right angles are not in a same vertical axis.

Abstract: The present invention relates to an integrated photonic and quantum system carried out by the combination and interconnection of Programmable Photonics Processing Blocks, implemented over a photonic chip that is capable of implementing one or multiple, simultaneous quantum and classical circuits with optical feedback paths and/or linear multiport transformations, by the appropriate programming of its resources and the selection of its input and output ports. The invention also relates to a quantum field-programmable photonic gate array (Q-FPPGA) comprising at least one programmable circuit based on tunable beam-splitters with independent coupling and phase-shifting configuration and peripheral high-performance building blocks enabling classical and quantum operations.

Abstract: Disclosed is a battery pack including a battery module having a plurality of battery cells, and a heat dissipation member provided in contact with a bus bar at a side surface of the battery module where electrode leads of the battery cells and the bus bar coupled to the electrode leads are disposed.

Abstract: Mechanisms are provided for optimizing an integrated circuit device design to obfuscate emissions corresponding to internal logic states of the integrated circuit device design. A first integrated circuit (IC) device design data structure is received and parsed to identify at least one instance of an obfuscation indicator in the data of the IC device design data structure. At least one IC logic element is marked, in the IC device design, which is associated with the at least one instance of the obfuscation indicator. At least one emission obfuscation optimization is applied to the marked at least one IC logic element to obfuscate emissions from the marked at least one IC logic element and generate an emissions obfuscated IC device design data structure. The emissions obfuscated IC device design data structure is output for fabrication of an IC device in accordance with the emissions obfuscated IC device design data structure.

Abstract: A method is provided for transforming a high-level language representation of a tensor computation graph into a low level language. The method includes assigning a tensor shape and a loop primitive. The method also includes generating, from the tensor computation graph and the assigned loop primitives, an initial loop structure. The method further includes positioning the layers of the tensor computation graph within a nested loop structure to provide a final loop structure, collapsing loops in the final loop structure, and mapping the collapsed loops to hardware components configured to execute the collapsed loops. The method can be applied to artificial intelligence (AI) and machine learning (ML) use cases for improved optimization of neural networks including compilation optimization for improving performance of simulations such as medical simulations, healthcare simulations, weather simulations, and/or simulations related to other complex systems, which can also support decision making.

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Abstract: Systems and methods are provided for A computer-implemented method for simulating behavior of an electrical circuit across a range of frequencies from 0 to fmax. A base function is determined that outputs magnitudes across the range of frequencies. A correction function is determined that outputs magnitudes across the range of frequencies. The base function is combined with the correction function to generate a circuit behavior model that provides magnitudes across the range of frequencies. Behavior of the electrical circuit is simulated using the circuit behavior model.

Abstract: A method of fabricating a semiconductor device may include designing a layout including first and second gate patterns, first and second dummy gate patterns, and third and fourth gate patterns sequentially arranged in a first direction; forming first to fourth sacrificial patterns and first and second dummy sacrificial patterns, which correspond to the first to fourth gate patterns and the first and second dummy gate patterns respectively, on a substrate using a photomask manufactured based on the layout; and performing an optical proximity correction on the layout. The optical proximity correction may include measuring distances between adjacent ones of the sacrificial and dummy sacrificial patterns in the first direction to provide measured distances, comparing a mean value of the measured distances with a mean value of target distances to obtain a first distance therebetween, and reducing a distance between the first and second dummy gate patterns by the first distance.

Abstract: A method of adding another circuit component with operations executable on an FPGA to an FPGA configuration, wherein the FPGA configuration already has at least one existing circuit component with operations executable on the FPGA, which is locally distributed in the FPGA configuration, includes synthesizing the further circuit component to obtain a further netlist, and distributed arranging of the further netlist taking into account the at least one existing circuit component in the FPGA configuration.

Abstract: A method for non-invasive characterisation of a cell for a battery is provided, the method comprising: measuring a magnetic field generated by the cell using a plurality of magnetic field sensors positioned adjacent to the cell, the measuring producing magnetic field sensor data, wherein the measuring is performed while the cell is in a passive state; determining current density profile data across the cell based on the magnetic field sensor data; and determining a condition of the cell using the current density profile data.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, an electronic design and applying one or more predefined rules to the electronic design. Embodiments may further include automatically generating a connectivity aware system signal flow diagram and causing a display of the connectivity aware system signal flow diagram at a graphical user interface.

Abstract: Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Abstract: A filter manufacturing method and a filter manufactured by the filter manufacturing method are disclosed. The filter manufacturing method includes designating a use mode in a resonator to a first resonance mode, in response to designating to the first resonance mode, setting a band selected from a designated first frequency band to a passband in the resonator, switching the use mode in the resonator from the first resonance mode to a second resonator mode, in response to switching to the second resonance mode, setting a band selected from the first frequency band except for the passband to a stopband in the resonator, and manufacturing a primary filter including the resonator to which the passband and the stopband are set.

Abstract: In some embodiments, a computer-implemented method for designing an integrated circuit using transistor placement optimization is provided. A computing system receives a specification for the integrated circuit. The specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors. The computing system determines an initial location and an orientation on a canvas for each transistor in the plurality of transistors. The computing system uses an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors. The computing system uses a local refinement technique to optimize the rough placement to generate a fine placement, and uses a routing technique to generate a routing for the fine placement to generate a completed design.

Abstract: The memory device includes a die with a first set of planes and a second set of planes. The planes are rectangular in shape with a major dimension and a minor dimension. The die includes a CMOS layer with at least one common peripheral circuitry area, and each of the planes includes a non-common peripheral circuitry area in the CMOS layer. Each plane of the first set of planes is oriented such that its major dimension extends in a first direction, and each plane of the second set of planes is oriented such that its major dimension extends in a second direction that is different than the first direction such that the non-common peripheral circuitry area of each plane is immediately adjacent the at least one common peripheral circuitry area in the CMOS layer.

Abstract: A neuromorphic system according to an embodiment of the invention includes an input signal section that generates an input signal, a synapse section that includes a plurality of synaptic units that receive the input signal and makes a current to flow according to a set weight, each of the plurality of synaptic units including a plurality of non-volatile memory cells capable of selectively storing a logical state, the non-volatile memory cells being arranged in a memory array that include input electrode lines and output electrode lines crossing each other, and generates an output signal for each output electrode line by the input signal, a digital calculation section that digitizes the output signal generated for each output electrode line and calculates a sum of the digitized output signals, and a controller section that controls the input signal section, the synapse section, and the digital calculation section, and the controller section designates the number of digitized digits for each output electrode li

Abstract: Systems and methods for operating quantum systems are described. A controller of a quantum system can generate a command signal. The quantum system can include quantum hardware having a plurality of qubits. An interface of the quantum system can control the quantum hardware based on the command signal to sample an input vector represented by the first set of qubits, where the input vector includes mixed states with different Hamming weights. The interface can control the quantum hardware to entangle the first set of qubits to the second set of qubits, where the second set of qubits represent a count of nonzero elements in the input vector. The interface can control the quantum hardware to generate an output vector based on the entanglement of the first set of qubits to the second set of qubits, where the output vector includes one or more states having a specific Hamming weight.

Abstract: According to one embodiment, a data analyzing apparatus acquires data containing the number N of analysis target samples (where N is an integer larger than or equal to 2). The apparatus performs a matrix factorization upon the data to factorize the data into the number K of basis samples and the number K of weights corresponding to the number K of basis samples (where K is an integer larger than or equal to 2), and fixes part of the K basis samples to specific basis samples in the matrix factorization.

Abstract: An integrated circuit includes a first region of the integrated circuit including a first set of pins extending in a first direction, being on a first level, and having a first width in a second direction different from the first direction. The first region has a first height in the second direction. An integrated circuit further includes a second region of the integrated circuit adjacent to the first region, the second region including a second set of pins extending in the first direction, being on a first level, being separated from the first set of pins in the second direction, and having a second width in the second direction, the first width being different from the second width. The second region has a second height in the second direction different from the first height, and the first level is a first metal layer of the integrated circuit.

Abstract: Globally placing a circuit design includes adjusting indicated capacity levels for placement bins associated with a target integrated circuit, based on first levels of demand for resources by instances in the circuit design in regions of the target IC. Region constraints restrict placement of the instances in the regions, and the regions include two or more two or more overlapping regions. Tracked levels of demand for resources in the placement bins are adjusted, after adjusting the indicated capacity levels, based on the indicated capacity levels, a target utilization level of the resources in the placement bins, and a current placement. The current placement of the instances is updated based on a density gradient of an electrostatics-based model of the tracked levels of demand, and repeating adjusting the tracked levels of demand and updating the current placement are repeated in response to the density gradient failing to satisfy a threshold.