Patents Examined by Jack Chiang
  • Patent number: 10977416
    Abstract: A method for cell swapping is provided. A location for swapping a first cell is determined. One or more legal positions for cell placement are determined at the location. A plurality of cells is determined for of the plurality of legal positions. A second cell from the plurality of cells is determined based on timing information associated with each of the plurality. The first cell is swapped with the second cell.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Yen-Hung Lin
  • Patent number: 10977421
    Abstract: A method of manufacturing an integrated circuit includes generating a first layout design based on design criteria, performing a color mapping between the first layout design and a standard cell layout design thereby generating a via color layout design, and manufacturing the integrated circuit based on the via color layout design. The first layout design has a first set of vias divided into sub-sets of vias based on a corresponding color indicating that vias of the sub-set of vias with a same color, and vias of the sub-set of vias with a different color. The standard cell layout design has a second set of vias arranged in standard cells. The via color layout design has a third set of vias including a portion of the second set of vias and corresponding locations, and color of the corresponding sub-set of vias.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Cheng Lin, Chih-Liang Chen, Chih-Ming Lai, Charles Chew-Yuen Young, Jiann-Tyng Tzeng, Kam-Tou Sio, Ru-Gun Liu, Shih-Wei Peng, Wei-Chen Chien
  • Patent number: 10970439
    Abstract: A System On Chip (SOC) current profile model for Integrated Voltage Regulator (IVR) co-design may be provided. A first current profile model may be extracted corresponding to an SOC at a first design stage of the SOC. Then it may be determined that an IVR and the SOC pass a first co-simulation based on the extracted first current profile model. Next, a second current profile model may be extracted corresponding to the SOC at a second design stage of the SOC. Then it may be determined that the IVR and the SOC pass a second co-simulation based on the extracted second current profile model. A third current profile model may be extracted corresponding to the SOC at a third design stage of the SOC. Then it may be determined that the IVR and the SOC pass a third co-simulation based on the extracted third current profile model.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: April 6, 2021
    Inventors: Haohua Zhou, Tze-Chiang Huang, Mei Hsu Wong
  • Patent number: 10970446
    Abstract: The disclosed approaches process a circuit design having first attributes associated with two or more signals or with sources of the two or more signals. The first attributes specify identifier values. The elements of the circuit design are placed on a target integrated circuit (IC), and timing analysis of the circuit design is performed after placing the elements of the circuit design. In response to the first attributes of the two or more signals or sources specifying equivalent identifier values and a path of at least one of the two or more signals or sources being timing-critical, equal numbers of one or more pipeline registers are inserted on paths of the two or more signals or sources.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: April 6, 2021
    Assignee: XLNX, INC.
    Inventors: Jeffrey H. Seltzer, Khang K. Dao, Sabyasachi Das
  • Patent number: 10955755
    Abstract: Disclosed herein are several methods of reducing one or more pattern displacement errors, contrast loss, best focus shift , tilt of a Bossung curve of a portion of a design layout used in a lithographic process for imaging that portion onto a substrate using a lithographic apparatus. The methods include adjusting an illumination source of the lithographic apparatus, placing assist features onto or adjusting positions and/or shapes existing assist features in the portion. Adjusting the illumination source and/or the assist features may be by an optimization algorithm.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 23, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Duan-Fu Stephen Hsu, Feng-Liang Liu
  • Patent number: 10951049
    Abstract: A control method for controlling a battery charging circuit having at least one switch, includes: generating a first difference signal based on a charging current feedback signal and a charging current reference signal; generating a second difference signal based on a battery voltage feedback signal and a battery voltage reference signal; based on a battery voltage, selecting one of the first and second difference signals, and a ground voltage as a third difference signal; generating a bias signal by proportionally integrating the third difference signal; comparing the sum of a system voltage feedback signal and a ramp signal with the sum of the bias signal and a system voltage reference signal and generating a comparison signal; generating a control signal to control the at least one switch of based on the comparison signal and a constant time period control signal.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: March 16, 2021
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Suhua Luo, Pengpeng Ma
  • Patent number: 10943039
    Abstract: An example multiply accumulate (MACC) circuit includes: a multiply-accumulator having an accumulator output register; a quantizer, coupled to the multiply accumulator; and a control circuit coupled to the multiply-accumulator and the quantizer, the control circuit configured to provide control data to the quantizer, the control data indicative of a most-significant bit (MSB) to least significant bit (LSB) range for selecting bit indices from the accumulator output register.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: March 9, 2021
    Assignee: XILINX, INC.
    Inventors: Ashish Sirasao, Elliott Delaye, Sean Settle, Zhao Ma, Ehsan Ghasemi, Xiao Teng, Aaron Ng, Jindrich Zejda
  • Patent number: 10929587
    Abstract: A method of designing a chip having an integrated circuit is provided. The method includes obtaining delta cell delays and delta net delays according to a process, voltage, and temperature (PVT) corner change with respect to a plurality of cells and a plurality of nets forming the integrated circuit; analyzing sensitivity with respect to a delay according to the PVT corner change of a plurality of paths in the integrated circuit, by using the delta cell delays and the delta net delays; determining N-number of sensitivity-critical paths among the plurality of paths based on a result of the analysis, wherein N is an integer greater than or equal to 0; and performing an engineering change order (ECO) based on a result of the determination.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-youn Kim, Eun-ju Hwang
  • Patent number: 10922456
    Abstract: The present embodiments relate to electrostatic discharge (ESD) simulation of integrated circuit designs. A netlist of the circuit design can be modified to include ESD protection devices and only essential non-ESD devices. The essential non-ESD devices can be determined based on whether a non-ESD device satisfies one or more of two conditions: (i) a least resistance path (LRP) value of at least one terminal of the non-ESD device from any port of the set of ports is less than a first threshold value or (ii) an effective resistance value between at least one terminal of the non-ESD device from any port of the set of ports is less than a second threshold value. The essential non-ESD devices are included in a reduced netlist in addition to the ESD protection devices. The ESD simulation is carried out on the reduced netlist, thereby reducing simulation time.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: February 16, 2021
    Assignee: Cadence Design Systems Inc.
    Inventors: Nandu Kumar Chowdhury, Rishab Dhawan, Parveen Khurana
  • Patent number: 10915690
    Abstract: Methods and systems for performing an electronic design. A layout of a via of an electronic design is obtained and a determination is made if the layout of the via satisfies one or more retargeting conditions, at least one of the retargeting conditions being that a first edge of a metal line is within a specified distance from a first edge of the via and a second edge of the metal line is within the specified distance from a second edge of the via, the first edge of the metal line being parallel to the first edge of the via and the second edge of the metal line being parallel to the second edge of the via; and reducing a resistance of the via by the layout of the via is retargeted in response to the retargeting conditions being satisfied.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Dongbing Shao, Yongan Xu, Shyng-Tsong Chen, Zheng Xu
  • Patent number: 10906421
    Abstract: A wireless automatic charging system for electric vehicles is disclosed, wherein the electric vehicle comprises a charging board, a Bluetooth device, a battery, as well as a battery management module electrically connected to the aforementioned charging board, Bluetooth device and battery and capable of detecting and recording the charging efficiency data concerning the charging board, and wherein the wireless automatic charging system for electric vehicles comprises a base seat, an air inflation and deflation device, a discharging board and a control console, wherein the battery management module in the electric vehicle can transfer the charging-related information of the electric vehicle to the control console via the Bluetooth module such, and adjust the distance between the charging board and the discharging board and/or charging power of the discharging board in accordance with the received charging efficiency data and the charging efficiency adjustment data.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 2, 2021
    Inventor: Chien-Chen Wu
  • Patent number: 10896278
    Abstract: An information processing apparatus includes a processor configured to accept feature information on a specification of a target circuit to be designed. The processor is configured to refer to first correspondence information in which a plurality of parameter values are associated with respective index values for each piece of feature information on specifications of respective circuits to be configured in an integrated circuit. The processor is configured to calculate, for each of a plurality of combinations of parameter values related to the accepted feature information, a sum of the index values associated with respective parameter values included in the relevant combination of parameter values. The processor is configured to select one or more combinations of parameter values from among the plurality of combinations of parameter values on basis of the calculated sums. The processor is configured to output the selected combinations of parameter values.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: January 19, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Michitaka Hashimoto, Ryo Mizutani
  • Patent number: 10884333
    Abstract: A method of design or verification for a self-assemblable block copolymer feature, the block copolymer feature including a first domain having a first polymer type and a second domain having a second polymer type, the method including, based on the length of the second polymer type or on an uncertainty in position of the first domain within the block copolymer feature calculated based on the length of the second polymer type, adjusting a parameter of the self-assembly process of a block copolymer feature or verifying a placement of a block copolymer feature.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: January 5, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Sander Frederik Wuister, Bart Laenens, Davide Ambesi
  • Patent number: 10885244
    Abstract: A test pattern includes first line patterns disposed at a first level, having discontinuous regions spaced apart by a first space, having a first width, and extending in a first direction. The test pattern includes a connection line pattern disposed at a second level and extending in the first direction, second line patterns disposed at the second level, branching from the connection line pattern, having a second width, and extending in a second direction perpendicular to the first direction. The test pattern includes via patterns disposed at a third level, having a third width, and formed around an intersection region having the first width of the first line pattern and the second width of the second line pattern. First pads are connected with the first line patterns. A second pad is connected with the connection line pattern.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Wook Hwang, Jong-Hyun Lee, Min-Soo Kang
  • Patent number: 10885257
    Abstract: Various embodiments provide for routing a network of a circuit design based on at least one of via spacing or pin density. For instance, some embodiments route a net of a circuit design (e.g., data nets, clock nets) by generating a congestion map based on modeling via spacing, modeling pin density, or some combination of both.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 5, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Gracieli Posser, Wing-Kai Chow, Mehmet Can Yildiz, Zhuo Li
  • Patent number: 10878167
    Abstract: A method including decomposing a conflict graph based on a number of masked to be used to manufacture a semiconductor device. The method further includes determining whether the decomposed conflict graph is a simplified graph based on a comparison between the decomposed conflict graph and a stored conflict graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device. The method further includes indicating that the conflict graph is colorable in response to a determination that the decomposed conflict graph is colorable.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Yun Cheng, Chin-Chang Hsu, Hsien-Hsin Sean Lee, Jian-Yi Li, Li-Sheng Ke, Wen-Ju Yang
  • Patent number: 10878151
    Abstract: The present disclosure discloses a glitch occurring point detection method to detect at least one glitch occurring point in an under-test circuit that includes the steps outlined below. An IC design file is retrieved to further retrieve a plurality of input nodes, at least one output node and a plurality of power nodes corresponding to the under-test circuit in the IC design file. Signals are fed to the input nodes and the power nodes such that a DC analysis is performed on a plurality of internal circuit nodes in the under-test circuit and a plurality of candidate floating points that do not have any charging or discharging path connected thereto are retrieved according to the DC analysis. Each of the candidate floating points capable of triggering the output node during the operation of the under-test circuit are determined to be the glitch occurring point.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: December 29, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Ying-Chieh Chen, Mei-Li Yu, Yu-Lan Lo
  • Patent number: 10878166
    Abstract: Techniques and systems for inserting repeaters in an integrated circuit (IC) design are described. Some embodiments can place a snapping region in the IC design, wherein the snapping region includes a predetermined arrangement of feasible grid regions and blocked grid regions, and wherein repeaters are allowed to be placed in feasible grid regions but not in blocked grid regions. Next, the embodiments can iteratively perform a set of operations, comprising: selecting a net from a set of nets; determining an initial location for inserting a repeater in the net; identifying an unoccupied feasible grid region in the first snapping region that is closest to the initial location; and inserting a repeater in the net in the unoccupied feasible grid region.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: December 29, 2020
    Assignee: Synopsys, Inc.
    Inventors: Kai-Ping Wang, Haiying Liu
  • Patent number: 10872190
    Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 22, 2020
    Inventors: Po-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
  • Patent number: 10860775
    Abstract: Various embodiments provide for assigning a clock pin to a clock tap within a circuit design based on connectivity between circuit devices of the circuit design. For some embodiments, an initial clock tap assignment, between a clock tap of a circuit design and a clock pin of the circuit design, is accessed as input, and a modified clock tap assignment (between the clock tap and another clock pin of the circuit design) can be generated based on one or more of the following considerations: a clock tap assignment should try to assign clock pins of connected circuit devices to the same clock tap; a clock tap assignment should try to assign clock pins of connected circuit devices having the critical timing problems; a clock tap assignment should try to assign clock pins of connected circuit devices to clock taps with longer common path length.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: December 8, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wing-Kai Chow, Zhuo Li