Abstract: A photomask includes at least one line pattern monitoring mark having unit blocks that include design line patterns. Each of the unit blocks includes three design line patterns sequentially offset in a second direction perpendicular to the first direction, the unit blocks include a first unit block and a second unit block adjacent to the first unit block, the second unit block is offset from the first unit block by a rounding length in the second direction and is spaced apart from the first unit block in the first direction. In a method of manufacturing an integrated circuit device, monitoring line patterns are formed using the photomask, and a line end profile error in the monitoring line patterns is determined based on a cross-sectional structure of the monitoring line patterns taken along a line extending through at least a portion of the monitoring line patterns in the first direction.

Abstract: A flat coil carrier may include a carrier body. The carrier body may include, on an axial front side, a groove spiral configured to receive a coil wire. The groove spiral may have an axially open groove opening and may include a plurality of radially consecutive groove sections. The plurality of radially consecutive groove sections may each have an axially open groove section opening of a plurality of groove section openings. The plurality of radially consecutive groove sections may each be separated from one another by a common separating wall section of a plurality of separating wall sections of the carrier body. At least one of the plurality of separating wall sections may protrude from the carrier body and may have at least one undercut section including a radially protruding protrusion such that an undercut for the coil wire is formed in the at least one undercut section.

Abstract: A method includes: accessing a first cell, where the first cell includes: a first active region and a second active; gate electrodes arranged in a second layer over the first layer; first conductive lines extending in the second layer; second conductive lines extending in the second layer; a third and a fourth conductive lines extending in a third layer over the second layer; and first gate vias arranged in a fourth layer and electrically coupled to the gate electrodes. The method also includes: determining a performance metric and a dielectric voltage stress level; and in response to the performance metric or the dielectric voltage stress level failing to fulfilling a specification, revising the first cell to generate a second cell by moving at least one of the first gate vias to be electrically coupled to the fourth conductive line.

Abstract: Scan chain optimization utilizing constrained single linkage clustering is disclosed. In an embodiment, a physical design tool identifies a placement of a plurality of latches in a circuit layout; generates, based on the placement, a set of latch clusters by applying constrained single-linkage agglomerative clustering to the plurality of latches; optimizes the set of latch clusters by redistributing latches across clusters; and generates a set of scan chains corresponding to the optimized set of latch clusters.

Abstract: A method and computer-implemented system for use with an electronic design automation (EDA) tool to optimize clock scheduling. Based on an initial timing and area optimized design for a logic circuit, an optimal set of clock anchor points on a clock tree for the logic circuit, and slack statistics for a plurality of elements in the logic circuit, are determined. Clock skews for the CAPs associated with the plurality of elements are then scheduled as a function of the slack statistics. A refined timing and area optimized design for the logic circuit is generated based on the clock skews, and the refined timing and area optimized design is utilized as input to a clock tree synthesis module of the EDA tool.

Abstract: Quantum computers, systems, apparatuses, and/or the like and corresponding methods for de-exciting coherent motional modes of an atomic object crystal confined by an atomic object confinement apparatus. One or more voltage sources are controlled to cause a waveform to be applied to an array of electrodes of the atomic object confinement apparatus. Application of the waveform to the array of electrodes causes each of the one or more transport operations to be performed on the respective atomic object crystal and causes de-excitation of at least one coherent motional mode of the respective atomic object crystal corresponding to the at least one of the one or more transport operations. The respective shim waveform configured to de-excite the at least one coherent motional mode may be determined based on a parameterized shim waveform and a calibration process for determining parameters corresponding to the atomic object confinement apparatus.

Abstract: The present disclosure provides a photomask and a method of forming a photomask, in which the photomask may obtain an optimized uniformity via a simplified process flow. The photomask includes a plurality of stair-like patterns parallel disposed with each other, wherein each of the stair-like patterns includes a plurality of first right angles at one side and a plurality of second right angle at another side opposite to the side, and each of the first right angles and each of the second right angles are not in a same vertical axis.

Abstract: The present invention relates to an integrated photonic and quantum system carried out by the combination and interconnection of Programmable Photonics Processing Blocks, implemented over a photonic chip that is capable of implementing one or multiple, simultaneous quantum and classical circuits with optical feedback paths and/or linear multiport transformations, by the appropriate programming of its resources and the selection of its input and output ports. The invention also relates to a quantum field-programmable photonic gate array (Q-FPPGA) comprising at least one programmable circuit based on tunable beam-splitters with independent coupling and phase-shifting configuration and peripheral high-performance building blocks enabling classical and quantum operations.

Abstract: Disclosed is a battery pack including a battery module having a plurality of battery cells, and a heat dissipation member provided in contact with a bus bar at a side surface of the battery module where electrode leads of the battery cells and the bus bar coupled to the electrode leads are disposed.

Abstract: Mechanisms are provided for optimizing an integrated circuit device design to obfuscate emissions corresponding to internal logic states of the integrated circuit device design. A first integrated circuit (IC) device design data structure is received and parsed to identify at least one instance of an obfuscation indicator in the data of the IC device design data structure. At least one IC logic element is marked, in the IC device design, which is associated with the at least one instance of the obfuscation indicator. At least one emission obfuscation optimization is applied to the marked at least one IC logic element to obfuscate emissions from the marked at least one IC logic element and generate an emissions obfuscated IC device design data structure. The emissions obfuscated IC device design data structure is output for fabrication of an IC device in accordance with the emissions obfuscated IC device design data structure.

Abstract: A method is provided for transforming a high-level language representation of a tensor computation graph into a low level language. The method includes assigning a tensor shape and a loop primitive. The method also includes generating, from the tensor computation graph and the assigned loop primitives, an initial loop structure. The method further includes positioning the layers of the tensor computation graph within a nested loop structure to provide a final loop structure, collapsing loops in the final loop structure, and mapping the collapsed loops to hardware components configured to execute the collapsed loops. The method can be applied to artificial intelligence (AI) and machine learning (ML) use cases for improved optimization of neural networks including compilation optimization for improving performance of simulations such as medical simulations, healthcare simulations, weather simulations, and/or simulations related to other complex systems, which can also support decision making.

Abstract: Process for determining defects in cells of a circuit is provided. A layout of a circuit is received. The layout comprises a first cell and a second cell separated by a boundary circuit. Bridge pairs for the first cell and the second cell is determined. The bridge pairs comprises a first plurality of boundary nodes of the first cell paired with a second plurality of boundary nodes of the second cell. Bridge pair faults between the bridge pairs are modeled. A test pattern for the bridge pair faults is generated.

Abstract: Systems and methods are provided for A computer-implemented method for simulating behavior of an electrical circuit across a range of frequencies from 0 to fmax. A base function is determined that outputs magnitudes across the range of frequencies. A correction function is determined that outputs magnitudes across the range of frequencies. The base function is combined with the correction function to generate a circuit behavior model that provides magnitudes across the range of frequencies. Behavior of the electrical circuit is simulated using the circuit behavior model.

Abstract: A method of fabricating a semiconductor device may include designing a layout including first and second gate patterns, first and second dummy gate patterns, and third and fourth gate patterns sequentially arranged in a first direction; forming first to fourth sacrificial patterns and first and second dummy sacrificial patterns, which correspond to the first to fourth gate patterns and the first and second dummy gate patterns respectively, on a substrate using a photomask manufactured based on the layout; and performing an optical proximity correction on the layout. The optical proximity correction may include measuring distances between adjacent ones of the sacrificial and dummy sacrificial patterns in the first direction to provide measured distances, comparing a mean value of the measured distances with a mean value of target distances to obtain a first distance therebetween, and reducing a distance between the first and second dummy gate patterns by the first distance.

Abstract: A method of adding another circuit component with operations executable on an FPGA to an FPGA configuration, wherein the FPGA configuration already has at least one existing circuit component with operations executable on the FPGA, which is locally distributed in the FPGA configuration, includes synthesizing the further circuit component to obtain a further netlist, and distributed arranging of the further netlist taking into account the at least one existing circuit component in the FPGA configuration.

Abstract: A method for non-invasive characterisation of a cell for a battery is provided, the method comprising: measuring a magnetic field generated by the cell using a plurality of magnetic field sensors positioned adjacent to the cell, the measuring producing magnetic field sensor data, wherein the measuring is performed while the cell is in a passive state; determining current density profile data across the cell based on the magnetic field sensor data; and determining a condition of the cell using the current density profile data.

Abstract: The present disclosure relates to a method for use with an electronic design. Embodiments may include receiving, using a processor, an electronic design and applying one or more predefined rules to the electronic design. Embodiments may further include automatically generating a connectivity aware system signal flow diagram and causing a display of the connectivity aware system signal flow diagram at a graphical user interface.

Abstract: Some embodiments provide a method for computing and displaying of minimum overlap for semiconductor layer interfaces, such as metal-via and metal-contact. The method leverages a machine-trained network (e.g., a trained neural network) to quickly, but accurately, infer the contours for the manufactured shapes across a range of process variations. The method also models the semiconductor process manufacturing layer-to-layer misalignment. The combined set of information (from the machine-trained network and from the modeling) is used by the method to compute the minimum overlap shapes at multiple layer interfaces. The method in some embodiments then uses the minimum overlap shapes to obtain an accurate calculation of the via or contact resistance.

Abstract: A filter manufacturing method and a filter manufactured by the filter manufacturing method are disclosed. The filter manufacturing method includes designating a use mode in a resonator to a first resonance mode, in response to designating to the first resonance mode, setting a band selected from a designated first frequency band to a passband in the resonator, switching the use mode in the resonator from the first resonance mode to a second resonator mode, in response to switching to the second resonance mode, setting a band selected from the first frequency band except for the passband to a stopband in the resonator, and manufacturing a primary filter including the resonator to which the passband and the stopband are set.

Abstract: In some embodiments, a computer-implemented method for designing an integrated circuit using transistor placement optimization is provided. A computing system receives a specification for the integrated circuit. The specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors. The computing system determines an initial location and an orientation on a canvas for each transistor in the plurality of transistors. The computing system uses an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors. The computing system uses a local refinement technique to optimize the rough placement to generate a fine placement, and uses a routing technique to generate a routing for the fine placement to generate a completed design.