Abstract: Methods for modifying power use of a semiconductor device include receiving, at one or more processors, an activity stream of a simulation of a semiconductor device, the activity stream comprising a stream of signals. Using the one or more processors, integrated circuit actions are recognized from the activity stream, each integrated circuit action representing an abstraction of work done by the semiconductor device. The processor(s) determine one or more values associated with the integrated circuit actions. A model of power use is generated for the semiconductor device, the model based at least in part on the recognized integrated circuit actions and the associated values. Based on an output of the model, power use of the semiconductor device is modified. Other methods and systems related to determining, modeling, and predicting power/energy use of semiconductor devices are also disclosed.

Abstract: Systems and methods for integrated circuit (IC) analysis using a multi-level data hierarchy implemented on a distributed compute and data infrastructure are described. An IC design may be represented using a set of storage areas, where each storage area may be stored in a contiguous block of storage and may correspond to a portion of the IC design. An analysis application may be executed on the IC design, where a subset of the set of storage areas that is used by the analysis application may be retrieved on-demand.

Abstract: Correction method of mask layout and mask containing corrected layout are provided. The method includes providing a target layout including a plurality of main patterns. Each main pattern includes a first side and an opposite second side. Extending directions of the first side and the second side are perpendicular to a first direction. Each main pattern also includes a third side and an opposite fourth side. Extension directions of the third side and the fourth side are perpendicular to a second direction. The second direction and the first direction are perpendicular to each other. The method also includes acquiring position information of each main pattern, and obtaining position information of auxiliary patterns adjacent to each main pattern. The method also includes, according to the position information of the auxiliary patterns adjacent to each main pattern, arranging the auxiliary patterns adjacent to each main pattern around each main pattern.

Abstract: A method and apparatus for generating a design for a 3D integrated circuit (3DIC) comprises extracting at least one design characteristic from a first data representation of a design for a 2D integrated circuit (2DIC) generated according to the design criteria required for the 3DIC. Components of the 3DIC are partitioned into groups (each representing one tier of the 3DIC) based on the extracted design characteristic. A second data representation of a 2DIC design is generated comprising multiple adjacent partitions each comprising the component groups for one tier of the 3DIC design together with inter-tier via ports representing locations of inter-tier vias. A placement for each partition is determined separately from a placement of corresponding components of the 2DIC represented by the original first data representation. This approach allows a 2DIC EDA tool to be used for designing a 3DIC.

Abstract: Systems and methods for performing depth-dependent oxidation modeling and depth-dependent etch modeling in a virtual fabrication environment are discussed. More particularly, a virtual fabrication environment models, as part of a process sequence, oxidant dispersion in a depth-dependent manner and simulates the subsequent oxidation reaction based on the determined oxidant thickness along an air/silicon interface. Further the virtual fabrication environment performs depth-dependent etch modeling as part of a process sequence to determine etchant concentration and simulate the etching of material along an air/material interface.

Abstract: A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: Embodiments disclosed herein describe switching logic in board-level interconnects and in the system-level interconnects that may provide bitwise dynamic routing and switching between corresponding board-level and system-level components. At board-level, a switching ASIC may receive input data through a backplane from an emulation ASIC in a first logic board and route any bit of the input data to any of the emulation ASIC in a second logic board. At system-level, a switching logic board containing a set of switching ASICs may be associated with a logic cluster and may dynamically route data bits from the emulation ASICs in the logic cluster to emulation ASICs to other logic clusters of the emulation system and/or target systems. Additionally, the switching logic board may dynamically route bits from the other logic clusters to the associated logic cluster.

Abstract: The present disclosure relates to systems and methods for floorplanning using machine learning techniques. Embodiments may include receiving an electronic design and analyzing the electronic design using a reinforcement learning agent. Embodiments may further include recommending a first action wherein the first action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the electronic design based upon, at least in part, the first action to generate an updated electronic design. Embodiments may further include analyzing the updated electronic design using the reinforcement learning agent and recommending a second action wherein the second action includes at least one of a place agent action, a via agent action, or a route agent action. Embodiments may also include updating the updated electronic design based upon the second action to generate a second updated electronic design.

Abstract: A method includes acquiring a vector data signal associated with a circuit design, performing a timing update to determine timing information for the circuit design, and identifying a glitch in the circuit design based on a shifted vector waveform. The timing information includes a signal delay associated with a cell of the circuit design. The shifted vector waveform is generated by shifting the vector data signal based on the timing information.

Abstract: A method for creating an allocation map, wherein the allocation map is created based on an FPGA source code, wherein the source code uses at least a first signal at a first location, wherein at least a first register is mapped to the first signal, wherein in the allocation map, the first signal and the first register are listed as mapped to one another, wherein a second signal is used at a second location in the FPGA source code, wherein it is automatically detected that the value of the second signal can be determined from the value of the first signal according to a first calculation rule, wherein in the allocation map, the second signal, the first register and the first calculation rule are listed as mapped to one another.

Abstract: Systems and methods are provided for a turnkey modular printed circuit board enclosure that is generated using a template generator. The template generator accepts a user input comprising an enclosure parameter, based on which a manufacturing file may be generated. The manufacturing file may be provided to a fabricator for fabricating the enclosure or the manufacturing file may be modified in a printed circuit board design environment to incorporate a printed circuit board into the enclosure. The printed circuit board may be a separate printed circuit board that is inserted into the enclosure or it may be embedded in a face of the enclosure.

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and performing a deadlock check on the electronic circuit design using a using a linear temporal logic property and a proof engine. Embodiments may further include analyzing a counterexample associated with the electronic circuit design for a loop escape condition, wherein analyzing includes proving a cover trace of a liveness obligation. If the loop escape condition is reachable from the counterexample, embodiments may include extracting one or more events associated with the loop escape condition and adding a waiver constraint to the deadlock check to force a no deadlock outcome.

Abstract: An electrical device comprising a reconfigurable integrated circuit that includes paired top electrodes and bottom electrodes separated from each other by an active layer.

Abstract: Examples provide a method of virtualizing a hardware accelerator in a virtualized computing system. The virtualized computing system includes a hypervisor supporting execution of a plurality of virtual machines (VMs). The method includes: receiving a plurality of sub-programs at a compiler in the hypervisor from a plurality of compilers in the respective plurality of VMs, each of the sub-programs including a hardware-description language (HDL) description; combining, at the compiler in the hypervisor, the plurality of sub-programs into a monolithic program; generating, by the compiler in the hypervisor, a circuit implementation for the monolithic program, the circuit implementation including a plurality of sub-circuits for the respective plurality of sub-programs; and loading, by the compiler in the hypervisor, the circuit implementation to a programmable device of the hardware accelerator.

Abstract: Systems and methods are provided for using an integrated circuit design tool to analyze timing requirements of a circuit design for an integrated circuit. A slack is calculated for a timing path in the circuit design that fails to satisfy a timing constraint. The slack is decomposed into multiple categories of delays in the timing path. The categories of delays for the slack may include intrinsic margin, clock skew, logic delay, and fabric interconnect delay. The logic delay may include local interconnect delay and logic circuit delay. The fabric interconnect delay may include delays in interconnect elements that are used to make connections between larger blocks of the logic circuits. Different optimization strategies are provided to solve the timing constraint failure for each of the different categories of slack breakdown. Slack profiles of the entire design in each of the four categories of slack are also provided.

Abstract: A system and method for generating simulation-friendly compact physical models for passive structures is disclosed. The method includes generating an impedance map specifying impedances at a plurality of frequencies corresponding to one or more port-pairs of a circuit component using a processor to extract a plurality of impedance values between the one or more port-pairs based on a first value for each parameter of a plurality of parameters of the circuit component. The method includes generating a second circuit representation model based on updating the plurality of impedance values between the one or more port-pairs based on a second value for one or more parameters of the plurality of parameters of the circuit component, and updating the second circuit representation model by tuning the updated plurality of impedance values of the between the one or more port-pairs based on a predetermined use context of the circuit component in a circuit.

Abstract: Methods and systems for performing fault injection testing on an integrated circuit hardware design.

Abstract: Variation-aware delay fault testing suitable for carbon nanotube field-effect transistor circuits can be accomplished using an electronic design automation tool that performs long path selection by generating random variation scenarios, wherein a random variation scenario (RVS) is an instance of an input netlist where values for a set of process parameters for each gate are chosen from a set of values for each process parameter of the set of process parameters for that gate, the set of values being sampled from a distribution of that particular process parameter for that gate and includes a nominal value for that particular process parameter; calculating a total delay through a path for each RVS; and selecting at least two paths having highest total delays for each fault site under random variations of the RVSs. Delay test patterns can then be generated for the selected paths.