Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and performing a deadlock check on the electronic circuit design using a using a linear temporal logic property and a proof engine. Embodiments may further include analyzing a counterexample associated with the electronic circuit design for a loop escape condition, wherein analyzing includes proving a cover trace of a liveness obligation. If the loop escape condition is reachable from the counterexample, embodiments may include extracting one or more events associated with the loop escape condition and adding a waiver constraint to the deadlock check to force a no deadlock outcome.

Abstract: An electrical device comprising a reconfigurable integrated circuit that includes paired top electrodes and bottom electrodes separated from each other by an active layer.

Abstract: Examples provide a method of virtualizing a hardware accelerator in a virtualized computing system. The virtualized computing system includes a hypervisor supporting execution of a plurality of virtual machines (VMs). The method includes: receiving a plurality of sub-programs at a compiler in the hypervisor from a plurality of compilers in the respective plurality of VMs, each of the sub-programs including a hardware-description language (HDL) description; combining, at the compiler in the hypervisor, the plurality of sub-programs into a monolithic program; generating, by the compiler in the hypervisor, a circuit implementation for the monolithic program, the circuit implementation including a plurality of sub-circuits for the respective plurality of sub-programs; and loading, by the compiler in the hypervisor, the circuit implementation to a programmable device of the hardware accelerator.

Abstract: Systems and methods are provided for using an integrated circuit design tool to analyze timing requirements of a circuit design for an integrated circuit. A slack is calculated for a timing path in the circuit design that fails to satisfy a timing constraint. The slack is decomposed into multiple categories of delays in the timing path. The categories of delays for the slack may include intrinsic margin, clock skew, logic delay, and fabric interconnect delay. The logic delay may include local interconnect delay and logic circuit delay. The fabric interconnect delay may include delays in interconnect elements that are used to make connections between larger blocks of the logic circuits. Different optimization strategies are provided to solve the timing constraint failure for each of the different categories of slack breakdown. Slack profiles of the entire design in each of the four categories of slack are also provided.

Abstract: A system and method for generating simulation-friendly compact physical models for passive structures is disclosed. The method includes generating an impedance map specifying impedances at a plurality of frequencies corresponding to one or more port-pairs of a circuit component using a processor to extract a plurality of impedance values between the one or more port-pairs based on a first value for each parameter of a plurality of parameters of the circuit component. The method includes generating a second circuit representation model based on updating the plurality of impedance values between the one or more port-pairs based on a second value for one or more parameters of the plurality of parameters of the circuit component, and updating the second circuit representation model by tuning the updated plurality of impedance values of the between the one or more port-pairs based on a predetermined use context of the circuit component in a circuit.

Abstract: Methods and systems for performing fault injection testing on an integrated circuit hardware design.

Abstract: Variation-aware delay fault testing suitable for carbon nanotube field-effect transistor circuits can be accomplished using an electronic design automation tool that performs long path selection by generating random variation scenarios, wherein a random variation scenario (RVS) is an instance of an input netlist where values for a set of process parameters for each gate are chosen from a set of values for each process parameter of the set of process parameters for that gate, the set of values being sampled from a distribution of that particular process parameter for that gate and includes a nominal value for that particular process parameter; calculating a total delay through a path for each RVS; and selecting at least two paths having highest total delays for each fault site under random variations of the RVSs. Delay test patterns can then be generated for the selected paths.

Abstract: An injection device is disclosed herein. The injection device is utilized to inject a liquid onto a test area of a semiconductor element. The injection device includes a base, a reservoir, a first testing pipe, a cleaning pipe and a liquid-draining pipe. The reservoir set on the base is provided with at least one connecting port and a dropping port, wherein the dropping port is against the test area of the semiconductor element. The first testing pipe, the cleaning pipe and the liquid-draining pipe are connected to at least one connecting port, wherein a first liquid is injected from the first testing pipe into the reservoir, and wherein the a cleaning liquid is injected from the cleaning pipe into the reservoir to clean the reservoir and the test area. The dropping port is utilized to drain off the first testing liquid and the cleaning liquid in the reservoir. A semiconductor testing system utilizing the injection device and its testing method are also provided herein.

Abstract: The present disclosure provides an electronic device, a method for generating a package drawing, and a computer readable storage medium. The electronic device includes a display device and a processor, the processor is configured to obtain a type of the element and size parameters corresponding to the element input by a user; determine a size and a position of each of pads corresponding to the element according to the type of the element and the size parameters corresponding to the element, and draw the pads; determine coordinates of endpoints of an entity layer corresponding to the element, and draw the entity layer; determine coordinates of endpoints of a height layer corresponding to the element, and draw the height layer; and determine coordinates of endpoints of a screen layer corresponding to the element, and draw the screen layer.

Abstract: A power supply device is provided with a disconnection means (AND element) for forcibly disconnecting a battery module from a series connection regardless of a gate signal. The power supply device forcibly disconnects partial battery modules from the series connection by the disconnection means (AND element) during powering by a power supply output, thereby performing control so that the accumulated discharge current amounts thereof per unit time become smaller than those of the other battery modules.

Abstract: A system and methods are disclosed that generate a physical roadmap for the connectivity of a network, such as a network-on-chip (NoC). The roadmap includes a set of possible positions for placement of edges and nodes, which are known to be an acceptable and good position for placement of these network elements, that honors the constraints of the network. These known positions are made available to the system for synthesis of the network and generating the connectivity and placement based on the physical roadmap.

Abstract: Systems, machine readable media and methods are described for analyzing one or more physical systems using techniques that recognize patterns in underlying data and use the patterns to efficiently compute outputs using the patterns to reduce computations. The physical systems can be simulated with an estimation (e.g., an estimated power versus time waveform) that can be efficiently computed and then the estimation can be analyzed to detect patterns in the data. The detected patterns can each be analyzed with, in one embodiment, higher accuracy than the estimation to provide data that can be combined across multiple instances of each pattern to provide a higher accuracy evaluation of the system with a lower computational overhead.

Abstract: A method for determining an electrical model of a string of photovoltaic modules from a characteristic I(V) of the string includes detecting a first linear zone and a second linear zone of the characteristic I(V); initialising the parameters of a non-by-pass electrical model corresponding to a first operating condition, called a non-by-pass condition; optimising the parameters of the non-by-pass electrical model from a reference characteristic I(Vref) equal to I(V), determining the parameters of the electrical model corresponding to a second operating condition, called a by-pass condition, in order to obtain a by-pass electrical model from the characteristic determining, from the characteristic I(V) the best model among the non-by-pass model and the by-pass model.

Abstract: A method including: computing a value of a first variable of a pattern of, or for, a substrate processed by a patterning process by combining a fingerprint of the first variable on the substrate and a certain value of the first variable; and determining a value of a second variable of the pattern based at least in part on the computed value of the first variable.

Abstract: A programmable device includes a functional module, a pre-allocation manager, a first connection line, and a second connection line, wherein the pre-allocation managers are connected by the first connection lines, and the pre-allocation managers are connected to the functional modules by the second connection lines; the first connection lines are used for data transmission between the pre-allocation mangers, and a transmission direction is determined according to the configuration; the second connection lines are used for data transmission between the pre-allocation managers and the functional modules; the pre-allocation mangers are used for data transmission between the first connection lines and for data transmission between the first connection lines and the functional modules. The first connection lines are configured as connection line segments for transmission in both directions, and a wiring structure is designed in a direction and shape meeting wiring requirements.

Abstract: Methods and systems for verifying a hardware design for a multi-stage component is stall independent. The multi-stage component is configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled by a set of one or more enable signals.

Abstract: Disclosed are a heating method for a rechargeable battery, a control unit and a heating circuit. The heating method comprises: determining a frequency value of a pulse current for heating the rechargeable battery in response to a heating command of the rechargeable battery; determining a current value of the pulse current according to the frequency value and an acquired state parameter of the rechargeable battery; judging whether the current value satisfies a preset heating demand; if the current value satisfies the heating demand, generating the pulse current under control according to the frequency value; if the current value does not satisfy the heating demand, re-determining the frequency value and the current value of the pulse current. The embodiments of the present disclosure further provide a control unit and a heating circuit.

Abstract: A method, a computer system, and a computer program product for scan chain wirelength optimization is provided. Embodiments of the present invention may include obtaining root nodes details from the root nodes. Embodiments of the present invention may include optimizing a connectivity of the root nodes. Embodiments of the present invention may include identifying a best start node and a best end node for each of the root nodes. Embodiments of the present invention may include optimizing child nodes in each of the root nodes. Embodiments of the present invention may include determining that a wirelength of a full tour is shorter or longer than a nearest neighbor. Embodiments of the present invention may include applying or skipping a solution.

Abstract: The present disclosure provides a photomask and a method of forming a photomask, in which the photomask may obtain an optimized uniformity via a simplified process flow. The photomask includes a plurality of stair-like patterns parallel disposed with each other, wherein each of the stair-like patterns includes a plurality of first right angles at one side and a plurality of second right angle at another side opposite to the side, and each of the first right angles and each of the second right angles are not in a same vertical axis.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. Embodiments may include receiving a netlist associated with an electronic design and performing genetic optimization on a portion of the netlist to identify and place one or more capacitors on a printed circuit board to minimize an impedance associated with a power plane. Embodiments may further include displaying, at a graphical user interface, a placement of the one or more capacitors, wherein the placement is based upon, at least in part, the performing.