Abstract: Based on a directive in a control file, a processor pre-routes, within a hierarchical integrated circuit design, a signal through one or more levels of design hierarchy between a signal source at a higher level of the design hierarchy and an entity instance at a lower level of the design hierarchy. The processor processes entity instances in the design hierarchy in a bottom-up manner to insert technology-specific structures into the hierarchical integrated circuit design. During the processing, the processor inserts into a particular entity instance of the design hierarchy a technology-specific structure and connects the technology-specific structure to the signal pre-routed to the particular entity instance by the pre-routing.

Abstract: A method of manufacturing a semiconductor device includes: generating a design data of the semiconductor device; and generating a design layout according to the design data. The design layout includes: a first power rail; a second power rail; a first cell including a first first-type active region and a first second-type active region, wherein a first cell height of the first cell is defined as a pitch between the first power rail and the second power rail; a second cell having a second first-type active region and a second second-type active region; and a third cell having a first portion and a second portion arranged in the second row and a fourth row, respectively.

Abstract: An integrated circuit simulation method is performed by a processor and includes: obtaining a register transfer level (RTL) waveform set obtained by performing an RTL simulation based on a circuit, where the circuit is generated in an RTL design stage and includes a register having an internal net and a data output port, and the RTL waveform set includes a first waveform corresponding to the data output port of the register; obtaining a netlist and delay information obtained by performing a logic synthesis based on the circuit, where the netlist includes a first node and a second node, the first node corresponds to the internal net of the register, and the second node corresponds to the data output port of the register; applying the first waveform to the first node; and triggering the register according to the delay information to obtain a second waveform at the second node.

Abstract: Methods and systems for verifying a hardware design for a multi-stage component configured to receive input data and generate output data by processing the input data at each of a plurality of successive stages wherein each stage is independently enabled is stall independent. For each stage from the second stage to the last stage: a relevant portion of the output data of an instantiation of the hardware design is verified as the same if the instantiation is in the same state when that stage is enabled in a cycle by any set of inputs and any subsequent stages are enabled in subsequent cycles by a first minimal sequence of inputs.

Abstract: A method and apparatus for identifying net text in a net list at each hierarchical level of the net list is disclosed. The identified net text is then associated with the hierarchical level in which the net text was found. Each cell in the net list can then be optimized by exploding the net list of at least one cell. Once exploded, the identified net text together with the associated hierarchical level of each progeny cell of each exploded cell is associated with the net list of the exploded cell.

Abstract: A method to place repeaters on existing structured routes based on user specified locations. Location can be specified in multiple ways. For example, a set of fixed repeating distances (starting from a driver), number of repeaters (spread evenly on net routing), an absolute cutline dissecting the existing nets routing (e.g., x or y coordinate measure from the origin of the cell), relative cutline dissecting the existing nets routing (e.g., x or y coordinate measured from the origin of the nets bounding box), etc. can specify location. A repeater legalization procedure allows a user to arrange repeaters in various forms thus legalizing them to meet specific design requirements. A preview mode is provided where results are presented in the form of annotations (e.g., cartoon drawings) displayed on a canvas (e.g., display screen) rather than in the form of real layout objects in a database.

Abstract: Dynamic port handling for circuit designs can include inserting, within a static isolated module of a circuit design, static drivers configured to drive isolated modules of reconfigurable module (RM) instances for inclusion in an RM of the circuit design. For each RM instance of a plurality of RM instances to be inserted into the RM, one or more additional ports can be inserted in the RM based on a number of isolated modules included in a current RM instance. Further, net(s) corresponding to the additional port(s) can be created. The circuit design, including the current RM instance, the additional port(s), and the net(s), can be placed and routed. Prior to the inserting and the performing place and route for a next RM instance to be inserted into the RM, the current RM instance can be removed from the RM along with the additional port(s) and the net(s).

Abstract: Methods and systems for performing fault injection testing on an integrated circuit hardware design.

Abstract: Systems, computer-implemented methods and/or computer program products are provided to facilitate operation of a quantum circuit on a set of qubits via providing and implementing decompositions of one or more unitary matrices. According to an embodiment, a system can implement a unitary matrix by providing and implementing a decomposition of the unitary matrix, to thereby facilitate operation of and/or operate a quantum circuit on a set of qubits. The system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a unitary matrix management component that decomposes a defined 4×4 unitary matrix into a defined circuit comprising a sequence of universal gates. The sequence of universal gates can be a same sequence for each defined 4×4 unitary matrix of a set of candidate 4×4 unitary matrices including the defined 4×4 unitary matrix.

Abstract: An IC device includes first and second cells adjacent each other and over a substrate. The first cell includes a first IO pattern along a first track among a plurality of tracks in a first metal layer, the plurality of tracks elongated along a first axis and spaced from each other along a second axis. The second cell includes a plurality of conductive patterns along corresponding different tracks among the plurality of tracks in the first metal layer, each of the plurality of conductive patterns being an IO pattern of the second cell or a floating conductive pattern. The first metal layer further includes a first connecting pattern along the first track and connects the first IO pattern and a second IO pattern of the second cell. The second IO pattern is one of the plurality of conductive patterns of the second cell and is along the first track.

Abstract: A method of forming an integrated circuit includes placing a first and a second standard cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height. Placing the first standard cell layout design includes placing a first set of pin layout patterns on a first layout level over a first set of gridlines, extending in a first direction, and having a first width in a second direction. Placing the second standard cell layout design includes placing a second set of pin layout patterns on the first layout level over a second set of gridlines, extending in the first direction, and having a second width in the second direction.

Abstract: A computing system implementing a design verification system can detect multiple analog design blocks in a circuit design describing an electronic device. The design verification system can generate equivalent networks for the analog design blocks using different sets of the parameters of the analog design blocks by selectively collapsing nodes and branches in the analog design blocks based on values of the different sets of the parameters. The equivalent networks can correspond to behavioral topologies of the analog design blocks having the different sets of the parameters. The design verification system can selectively compile a subset of the analog design blocks into multiple compiled variant models based on a comparison of the equivalent networks. The design verification system can include an analog simulator to simulate the analog design blocks in the circuit design using the compiled variant models.

Abstract: A method includes acquiring timing analysis data associated with a cell and activity data of one or more inputs of the cell, determining a glitch toggle rate for an output of the cell based on the activity data of the one or more inputs of the cell and the timing analysis data, and estimating a glitch power based on at least the glitch toggle rate.

Abstract: Described is an apparatus for supporting Over-The-Air Hardware Updates comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may be operable to be fastened and electrically coupled in one or more regions to one or more respectively corresponding semiconductor dies. The second circuitry may be operable to configure the one or more regions of the first circuitry. The third circuitry may be operable to provide a set of wirelessly-received configuration instructions to the second circuitry.

Abstract: A system generates a mask for a circuit design while enforcing symmetry and consistency across random areas of the mask. The system builds a mask solutions database mapping circuit patterns to mask patterns. The system uses the mask solutions database to replace circuit patterns of the circuit design with mask patterns. The system identifies properties in circuit patterns of the circuit design and enforces the same property in the corresponding mask patterns. Examples of properties enforced include symmetry within circuit patterns and similarity across circuit patterns. The system combines mask patterns in different regions of the circuit and resolves conflicts that occur when there are multiple masks within a region.

Abstract: A method of designing an integrated circuit (IC) device includes identifying, with a processor, a pin failing a test to determine an antenna effect, identifying, with the processor, a net corresponding to the identified pin failing the test to determine the antenna effect, and creating, with the processor, an engineering change order (ECO) script based on the identified net to insert a diode to address the antenna effect.

Abstract: The disclosure provides a system to simulate a simulated noise on the power zone block of a substrate. The system comprises a signal trace and a signal generating circuit. The signal trace is disposed adjacent to the power zone block. The signal generating circuit is electrically coupled to the signal trace, configured to transmit an alternating current signal over the signal trace. The alternating current signal transmitted over the signal trace is configured to induce a simulated noise on the power zone block, and a waveform of the simulated noise is determined by a frequency of the alternating current signal.

Abstract: A chip includes a first circuitry and a second circuitry. The first circuitry includes first circuits which have first power consumption at a point of time. The second circuitry includes second circuits which have second power consumption at the point of time, and the first power consumption is higher than the second power consumption. At least one of the first circuits and at least one the second circuits are alternately arranged, in order to lower an operating temperature of the plurality of first circuits at the point of time.

Abstract: This application provides a battery protection circuit, a battery protection board, a battery, and a terminal device. The battery protection circuit includes: a first detection unit; a second detection unit; and a current detection element, a first switch unit, and a second switch unit that are configured to connect to an electrochemical cell in series, to form a charging loop or a discharging loop. The first detection unit corresponds to the first switch unit, and the second detection unit corresponds to the second switch unit. Each detection unit controls, based on a detected voltage at two ends of the same current detection element, a corresponding switch unit to be closed or opened, so as to control the loop to be closed or opened.

Abstract: A method for dynamically generating or interacting with an electromagnetic field includes providing a spatial array of conductive segments, a switching device operable on each of the conductive segments to either allow or block transmission of an electrical signal and a control device operable on the switching device. A sequence of the conductive segments are connected to form a conductive path where each segments intersects with at least two different ones of the conductive segments at a node. The switching device operates to connect a selected first one of the conductive segments with a selected second one of the conductive segments to form the sequence according to a logic signal from the control device. Power is supplied to the conductive path to produce an electromagnetic field which depends at least in part on the spatial arrangement of the connected sequence of the conductive segments.