Patents Examined by Jack Lane
  • Patent number: 7797486
    Abstract: The storage system includes a disk controller for receiving write commands from a computer, and a plurality of disk devices in which data is written in accordance with the control of the disk controller. The size of the first block which constitutes the data unit handled in the execution of the input/output processing of the data in accordance with the write command by the disk controller is different from the size of the second block which constitutes the data unit handled in the execution of the input/output processing of data by the plurality of disk devices. The disk controller issues an instruction for the writing of data to the disk devices using a third block unit of a size corresponding to a common multiple of the size of the first block and the size of the second block.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: September 14, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Ikuya Yagisawa, Naoto Matsunami
  • Patent number: 7769955
    Abstract: A data processing apparatus is provided wherein processing circuitry executes multiple program threads including at least one high priority thread and at least one lower priority thread. Instructions required by the threads are retrieved from a cache memory hierarchy comprising multiple cache levels. The cache memory hierarchy includes a bypass path for omitting a predetermined level of the cache memory hierarchy when performing a lookup procedure for a required instruction and for bypassing said predetermined level of the cache memory hierarchy when returning said required instruction to said processing circuitry. The bypass path is used by default when the requested instruction is for a lower priority thread.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: August 3, 2010
    Assignee: ARM Limited
    Inventors: Emre Özer, Stuart David Biles
  • Patent number: 7415583
    Abstract: A method and apparatus to free at least a portion of memory space of a memory device from at least a portion of a stored data block, wherein the freeing is based on the block sequence number of the stored data block and a quality indicator value related to at least a portion of the stored data block. The apparatus may include a receiver to receive at least the portion of the data block transmitted according to an error correction scheme.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: August 19, 2008
    Assignee: Marvell World Trade Ltd.
    Inventors: Moti Altahan, Sharon Levy
  • Patent number: 7415570
    Abstract: A tape drive apparatus includes a data transfer apparatus for transferring data to and from a tape media loaded in the tape drive apparatus, a first port for communicating with the data transfer apparatus in a tape drive mode, a second port for communicating with the data transfer apparatus in an optical storage device mode, and an emulation apparatus for permanently emulating an optical storage device at the second port for enabling an external device to access the data transfer apparatus, via the second fort, in the optical storage device mode.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: August 19, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Rhys Wyn Evans, Alastair Michael Slater, Duncan Wakelin
  • Patent number: 7401183
    Abstract: A system for authenticating a memory card including: a memory card host device including a plural area authentication module which judges whether the memory card has plural storage areas, and an area switching module which switches a storage area subject to access a different storage area from among plural storage areas; a memory card including plural storage areas, at least one internal register which retains a value indicating the number of storage areas, and a controller which transmits the value indicating the number of the storage areas to the memory card host device; and a bus which transmits and receives data between the memory card host device and the memory card.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: July 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takaya Suda
  • Patent number: 7395377
    Abstract: A technique for determining when to destage write data from a fast, NVS of a computer system from an upper level to a lower level of storage in the computer system comprises adaptively varying a destage rate of the NVS according to a current storage occupancy of the NVS; maintaining a high threshold level for the NVS; maintaining a low threshold level that is set to be a predetermined fixed amount below the high threshold; setting the destage rate of the NVS to zero when the NVS occupancy is below the low threshold; setting the destage rate of the NVS to be maximum when the NVS occupancy is above the high threshold; linearly increasing the destage rate of the NVS from zero to maximum as the NVS occupancy goes from the low to the high threshold; and adaptively varying the high threshold in response to a dynamic computer storage workload.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: July 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Binny S. Gill, Dharmendra S. Modha
  • Patent number: 7392340
    Abstract: A disk drive is disclosed comprising a disk, a head actuated over the disk, a host interface for receiving disk access commands from a host, a command queue for queuing the disk access commands, and a stream detection engine for evaluating the disk access commands to detect a plurality of streams accessed by the host. The stream detection engine maintains a stream data structure for each detected stream, wherein the stream data structure comprises a frequency counter for tracking a number of disk access commands associated with the stream out of a predetermined number of consecutive disk access commands received from the host. A disk controller selects one of the streams for servicing in response to the frequency counters.
    Type: Grant
    Filed: March 21, 2005
    Date of Patent: June 24, 2008
    Assignee: Western Digital Technologies, Inc.
    Inventors: Quoc Dang, Joseph C. S. Liu
  • Patent number: 7392337
    Abstract: A system for implementing a memory subsystem command interface, the system including a cascaded interconnect system including one or more memory modules, a memory controller and a memory bus. The memory controller generates a data frame that includes a plurality of commands. The memory controller and the memory module are interconnected by a packetized multi-transfer interface via the memory bus and the frame is transmitted to the memory modules via the memory bus.
    Type: Grant
    Filed: July 20, 2007
    Date of Patent: June 24, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kevin C. Gower, Warren E. Maule
  • Patent number: 7386699
    Abstract: A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Internet Protocol) packets as payloads. The alignment module prefixes non-data bits to the frame header to shift the IP payload into a position in the memory regions such that the IP payload is aligned with the memory boundaries. The number x of non-data bits is determined according to x=m*c+p, where m is the bit depth of memory regions, n is the length of a header, p is the non-zero remainder of the ratio n/m, and c is an integer.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: June 10, 2008
    Assignee: Marvell International Ltd.
    Inventor: Nafea Bishara
  • Patent number: 7386695
    Abstract: A storage controller, cooperable with host computer apparatus, and a plurality of controlled storage apparatus, comprises a host write component operable to write a data object to a source data image at one of the plurality of controlled storage apparatus; a first copy component responsive to a first metadata state and operable to control copying of the data object to a first target data image at one of the plurality of controlled storage apparatus; a second copy component responsive to a second metadata state and operable to perform one of: controlling copying of the data object to a second target data image at one of the plurality of controlled storage apparatus; and causing the first copy component to perform copying of the second target data image to the first target data image.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: June 10, 2008
    Assignee: International Business Machines Corporation
    Inventor: Carlos F. Fuente
  • Patent number: 7380074
    Abstract: Provided are a method, system and program for selecting storage clusters to use to access storage. Input/Output (I/O) requests are transferred to a first storage cluster over a network to access storage. The storage may be additionally accessed via a second storage cluster over the network and both the first and second storage clusters are capable of accessing the storage. An unavailability of a first storage cluster is detected when the second storage cluster is available. A request is transmitted to hosts over the network to use the second storage cluster to access the storage. Hosts receiving the transmitted request send I/O requests to the storage via the second storage cluster if the second storage cluster is available.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: May 27, 2008
    Assignee: International Business Machines Corporation
    Inventor: Timothy C. Pepper
  • Patent number: 7376805
    Abstract: Systems and methods for asynchronous backup of virtual disks in a distributed storage array are disclosed. An exemplary method may comprise receiving an IO stream at the virtual disks in the distributed storage array, writing data to one or more storage cells of the virtual disks in the distributed storage array, and logging completed writes in a first batch for each of the one or more storage cells. The method also comprises establishing a consistency point in the IO stream, terminating logging to the first batch for each of the one or more storage cells at the consistency point and logging completed writes after the consistency point to a new batch for each of the one or more storage cells. The method also comprises transferring writes logged in the first batch to at least one remote storage so that the at least one remote storage is crash consistent.
    Type: Grant
    Filed: April 21, 2006
    Date of Patent: May 20, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Christopher Stroberger, Susan Spence
  • Patent number: 7373470
    Abstract: In a storage system that executes multi-target remote copying, the identity of data across two secondary storage subsystems may be quickly and flexibly ensured. The storage system includes a first storage subsystem that has a first storage area and multiple second storage subsystems that each have a second storage area to store duplicate data for data stored in the first storage area. In this storage system, a write process that writes write data to the first storage area is executed. In response to the write process, the write data is copied to the second storage area of each second storage subsystem. Furthermore, a write section that the copy information belongs to, wherein the copy information that corresponds to the write process, is determined for each write process. In addition, history information regarding each executed copy operation is created for each write section to which the copy information used for such operation belongs.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: May 13, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Kenta Ninose, Hiroshi Arakawa, Yasutomo Yamamoto
  • Patent number: 7370137
    Abstract: Address translation for a source and destination of the data that utilizes different page tables. A direct memory access (DMA) engine is used as a memory-to-memory copy engine by utilizing a page-table walk and address translation for a source side of the copy, and an independent page-table walk and address translation for a destination side of the copy.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: May 6, 2008
    Assignee: Intel Corporation
    Inventor: Greg Regnier
  • Patent number: 7366860
    Abstract: A storage device is capable of sequentially inputting a command, which includes address information and attached information, from an information processor through an input/output unit. The storage device includes a storage unit for storing data; an extractor for extracting the address information and the attached information from an input command inputted through the input/output unit; a generator for, in response to input of the input command, generating transition information that transitions according to rules using an initial value; a comparator for determining whether the attached information and the transition information agree with each other; and an output controller for, only when the attached information and the transition information agree with each other, outputting storage data out of the data, which corresponds to the address information extracted by the extractor, through the input/output unit.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: April 29, 2008
    Inventor: Kumiko Mito
  • Patent number: 7366820
    Abstract: A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1A and a chip-enable control unit 61. The second-cache control unit 1A receives an access request for an access to the second cache and designates some of the RAMs, which need not operate, in accordance with the type or address of the access request, or both. The chip-enable control unit 61 outputs an intra-macro stop-instructing signal to the RAMs that have been designated by the second-cache control unit 1A.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: April 29, 2008
    Assignee: Fujitsu Limited
    Inventors: Mie Tonosaki, Tomoyuki Okawa
  • Patent number: 7363441
    Abstract: A portable storage apparatus capable of freely changing a data bus width and a method of setting the data bus width of the apparatus are provided, where the portable storage apparatus has at least one command line and a plurality of data lines and includes a non-volatile memory, a command packet decoder, and a control unit such that the non-volatile memory stores data, the command packet decoder receives command packets through a command line and outputs command information by decoding the received command packets, the command packet decoder receives a data transmit command packet or a data request command packet and outputs a write command or a read command, address information, and data bus width information, the control unit performs a control operation in response to the command information and selects all or some of the plurality of data lines in response to the data bus width information and receives or transmits the data through the selected data line, and controls data writing or reading of the non-vo
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: April 22, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myoung-kyoon Yim, Sang-kil Lee
  • Patent number: 7363459
    Abstract: A method of storing data includes the steps of storing data comprising the steps of identifying respective lifetimes of each member of an indexed collection of data elements, each of the data elements referenceable in a data index space representing a set of valid data element indices; identifying a set of pairs of the data elements having overlapping lifetimes; and generating a mapping from the data index space to an address offset space based on the set of pairs of the data elements having the overlapping lifetimes.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: April 22, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert S. Schreiber, Alain Darte
  • Patent number: 7363440
    Abstract: A system and method for dynamically accessing memory under normal operating conditions without interrupting computer system clocks that are otherwise executing. At least a memory access mode and a memory address(es) are scanned into a control scan chain from a maintenance system. When the scan is complete, the information is collectively transferred to an access register bank. Based on the control signals, a selection multiplexer selects the information from the control scan chain provided by the maintenance system as opposed to standard signals generated by the computer system. Memory control input signals are generated in response to a clock trigger signal, and the read or write data transfer is initiated.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: April 22, 2008
    Assignee: Unisys Corporation
    Inventor: Paul S. Neuman
  • Patent number: 7363454
    Abstract: Techniques are provided for allocating storage space to a storage pool. A request for storage space for the storage pool is received. A list of locations associated with the storage pool is obtained, wherein the locations are capable of spanning multiple file systems or multiple directories within a single file system. One or more allocation techniques are applied to select one or more locations at which storage space is to be allocated. The storage space is allocated at the selected one or more locations.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: April 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: David Maxwell Cannon, Colin Scott Dawson, Barry Fruchtman, Charles Alan Nichols