Abstract: A memory access technique, in accordance with one embodiment of the present invention, includes caching segmentation data. The technique utilizes a separate memory for storing a plurality of context specifiers and an MMU. The MMU includes an on-chip cache and a segmentation unit. The MMU receives a location of a particular context specifier and a corresponding context index for each of one or more of the plurality of context specifiers stored in the separate memory. The segmentation unit retrieves the particular context specifier and caches it locally. The segmentation unit also binds the cache location of the particular context specifier to the corresponding context index. After caching one or more context specifiers and generating a corresponding binding, the segmentation unit may receive a memory access request that includes a given context index. A given context specifier that is cached locally is accessed by the segmentation unit using the context index to get a base address.

Abstract: A method of accessing memory, in accordance with one embodiment, includes receiving a memory access request that includes a virtual address. An address of a given page table is determined utilizing a page directory stored in a particular one of a plurality of computing device-readable media. A given one of the plurality of computing device-readable media that stores the given page table is determined from a table aperture attribute in the page directory. A given physical address of a page is determined utilizing the given page table stored in the given computing device-readable media. A corresponding one of the plurality of computing device-readable media that stores the page is determined from a page aperture attribute in the given page table. The corresponding computing device-readable media at the given physical address is then accessed.

Abstract: In a storage medium, an address space is defined which is divided into a first area and a second area. According to the invention, at least one file is stored on the medium which is split into small data packets and large data packets. All small data packets are stored on said first area, and all large data packets are stored on said second area. A single file allocation table (FAT) is used and is small by having one entry per data packet.

Abstract: A method of assigning a multi-dimensional physical address to a tape-based data storage device is provided. The method includes accessing a first signal from a first communication path electrically coupled to a first tape-based data storage device, wherein the first signal indicates a physical position of the first tape-based data storage device with respect to a first axis. The method further includes accessing a second signal from a second communication path electrically coupled to the first tape-based data storage device, wherein the second signal is associated with a physical position of the first tape-based data storage device with respect to a second axis.

Abstract: A multipath accessible semiconductor memory device having a mailbox area and a mailbox access control method thereof are provided. The semiconductor memory device includes N number of ports, at least one shared memory area allocated in a memory cell array, and N number of mailbox areas for message communication. The at least one shared memory area is operationally connected to the N number of ports, and is accessible through a plurality of data input/output lines to form a data access path between the at least one shared memory area and one port, having an access right to the at least one memory area, among the N number of ports. The N number of mailbox areas are provided in one-to-one correspondence with the N number of ports and are accessible through the plurality of data input/output lines when an address of a predetermined area of the at least one shared memory area is applied to the semiconductor memory device. An efficient layout of mailboxes and an efficient message access path can be obtained.

Abstract: A memory system includes a multi-bit flash memory device and a flash controller configured to control the multi-bit flash memory device. The flash controller is configured to output a series of commands, pointers, and addresses to the multi-bit flash memory device for read/program operations.

Abstract: An information recording medium, recording and/or reproducing apparatuses, and recording and/or reproducing methods which enable effective management of a last data recording address of a data area of the information recording medium. The information recording medium includes a data area for recording user data, temporary recording management information for managing a data recording status of the data area and temporary disc management information for managing the information recording medium, wherein the temporary disc management information includes first information regarding a last recorded location of data in the data area and second information regarding whether the information regarding the last recorded location is consistent with an actual last recorded location of the data area.

Abstract: A write command is received from a host computer at a disk drive having a disk. The write command is associated with a data block and a logical block address of the data block, and a logical sector size of the data block is smaller than a physical sector size of a physical sector on the disk associated with the logical block address. The data block is written to a staging sector located in non-volatile media of the disk drive based at least in part on the logical sector size being smaller than the physical sector size. A write response is sent to the host computer, the write response indicating that the write command has been completed. After sending the write response to the host computer, the data block is written to the physical sector on the disk.

Abstract: The present invention discloses an electronic device using a memory to expand storage capacity, and the device includes a main board and a data storage module. The main board includes at least one interface card slot, and the data storage module includes at least one storage interface card, and a plurality of memory slots disposed on the storage interface card for movably inserting a memory. The memory is for storing data, and the storage interface card is inserted into the interface card slot. With the memory slot on the storage interface card, the memory can be expanded conveniently, and the storage capacity can be increased dynamically as needed. The invention also enhances the security, performance, and vibration resisting function of the data storage.

Abstract: To optimize performance and power consumption of a storage system having many disk drives, the storage system contains a plurality of volumes. A first number of the volumes belong to a first volume set. The first number of the remaining volumes belong to a second volume set. The volumes that belong to the first volume set are allocated dispersedly to a second number of disk drives. The volumes that belong to the second volume set are allocated dispersedly to a third number of disk drives, the third number being larger than the second number. A computer selects one of the first volume set and the second volume set based on a predetermined condition to store data dispersedly in the volumes belonging to the selected volume set. The computer stops spinning of disks in the disk drives to which none of the volumes belonging to the selected volume set are allocated.

Abstract: An apparatus usable with a flash memory as storage and a method of operating the same are provided, which can provide an optimized architecture to a flash memory through combination of a flash transition layer (FTL) with a database. The apparatus includes a flash memory, a device driver to manage a mapping table between logical addresses and physical addresses in accordance with a data operation in the flash memory, and a control unit to perform data recovery of the flash memory by requesting the mapping table through an interface provided by the device driver.

Abstract: A method may include counting the number of times each of a plurality of entries in a content addressable memory (CAM) matches one or more searches; grouping entries in the CAM into a first subset and a second subset based on the number of times each of the plurality of entries in the CAM matches one or more searches; and searching the first subset for a matching entry and, if no matching entry is found, searching the second subset for the matching entry.

Abstract: Proposed is a storage system capable of preventing the compression of a cache memory caused by data remaining in a cache memory of a storage subsystem without being transferred to a storage area of an external storage, and maintaining favorable I/O processing performance of the storage subsystem. In this storage system where an external storage is connected to the storage subsystem and the storage subsystem provides a storage area of the external storage as its own storage area, provided is a volume for saving dirty data remaining in a cache memory of the storage subsystem without being transferred to the external volume. The storage system recognizes the compression of the cache memory, and eliminates the overload of the cache memory by saving dirty data in a save volume.

Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

Abstract: A method, system, and apparatus of minimizing configuration of changes in a fabric-based data protection solution. In one embodiment, a method includes configuring a switch such that a write request to a primary storage device is transferred through a virtual initiator in the switch to the primary storage device and to a secondary storage device, and configuring the switch such that a read request from the secondary initiator of a data in the primary storage device appears as though the read request is coming from a physical initiator rather than the secondary initiator (e.g., such that system protocol may be bypassed because the switch intercepts a response having the data from the primary storage device through a virtual target which uses the virtual initiator of the switch to communicate the data to the secondary initiator rather than the physical initiator).

Abstract: A method may include counting the number of times each of a plurality of entries in a content addressable memory (CAM) matches one or more searches; grouping entries in the CAM into a first subset and a second subset based on the number of times each of the plurality of entries in the CAM matches one or more searches; and searching the first subset for a matching entry and, if no matching entry is found, searching the second subset for the matching entry.

Abstract: A computerized system is booted from a flash memory device configured to always operate one or more of its blocks only in a M-bit-per-cell mode and the rest of its blocks in a N>M-bit-per-cell mode. When the system is powered up, an initialization program is retrieved from the M-bit-per-cell block(s), corrected for errors using a first error correction method, and executed. Data accessed subsequently from the N-bit-per-cell blocks are corrected using an error correction method that corrects more errors per block than the first error correction method.

Abstract: A communication interface, coupling a controller device to one or more memory devices, provides a high-voltage reset interface. The high-voltage reset interface provides a high-voltage signal to reset the one or more memory devices. The high-voltage reset interface is implemented using a single interconnect line. The reset voltage signal is greater than a maximum voltage representing a high logic value. The communication interface may also include a bi-directional data and address interface that is used to send address, data, and commands between the controller device and the one or more memory devices. A method of transferring information between the controller device and the one or more non-volatile memory devices includes resetting the one or more non-volatile memory devices by asserting a high-voltage signal on the high-voltage reset interface and sending a command from the controller device to the one or more non-volatile memory devices via the data and address interface.

Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Abstract: A technique for performing stream detection and prefetching within a cache memory simplifies stream detection and prefetching. A bit in a cache directory or cache entry indicates that a cache line has not been accessed since being prefetched and another bit indicates the direction of a stream associated with the cache line. A next cache line is prefetched when a previously prefetched cache line is accessed, so that the cache always attempts to prefetch one cache line ahead of accesses, in the direction of a detected stream. Stream detection is performed in response to load misses tracked in the load miss queue (LMQ). The LMQ stores an offset indicating a first miss at the offset within a cache line. A next miss to the line sets a direction bit based on the difference between the first and second offsets and causes prefetch of the next line for the stream.