Abstract: A system and method for address space layout randomization (“ASLR”) for a Windows operating system is disclosed. The address space layout includes one or more memory regions that are identified and then a particular implementation of the system randomizes the identified memory region in order to prevent any software vulnerabilities.

Abstract: A method and related computer program product for combining resources of multiple RAID controllers and managing them as a single entity, comprising searching the RAID controllers for the most appropriate version of the firmware to be executed, determining whether a more appropriate version of the firmware was previously loaded into system memory, unloading inappropriate versions of the firmware, loading the most appropriate version of the firmware and initializing all RAID controllers as a commonly managed entity having combined resources.

Abstract: Storage network arrangements effecting a method including: acquiring information on the real volumes, and port information on the physical devices in which the real volumes reside; creating virtual volumes being linked to the real volumes, based on the information on the real volumes; forming one or more virtual volume groups by combining the virtual volumes, based on the port information, in such a way that the virtual volumes and the virtual volume groups in which the virtual volumes reside have a virtual-volume-to-virtual-volume-group configuration which is identical to a real-volume-to-physical-device configuration of the real volumes and the physical devices in which the real volumes reside; and establishing the created virtual volume groups in the upper storage apparatus.

Abstract: A plurality of storage devices, provided in a storage system, comprise not less than two member storage devices, which are storage devices provided as members of a RAID group, and a spare storage device, which is not a member of the RAID group. A controller, provided in the storage system, uses the spare storage device to carry out the changing of the RAID level of the RAID group from a first RAID level to a second RAID level.

Abstract: A memory system includes a multi-bit flash memory device and a flash controller configured to control the multi-bit flash memory device. The flash controller is configured to output a series of commands, pointers, and addresses to the multi-bit flash memory device for read/program operations.

Abstract: A controller sets a specified time which is a time that specifies a time in the future relative to the current time for all of one or more secondary storage systems. The respective secondary storage systems have a logical volume for backup (BVOL), and set a backup preparation end state when a journal up to a specified time has been established, and report information showing a preparation end state to the controller. The controller issues a backup command to all of the one or more secondary storage systems when information showing a preparation end state is reported from all of the one or more secondary storage systems.

Abstract: Embodiments of the invention may generally provide techniques that allow mapping of memory devices in a multi-chip package (MCP) to memory segments of an address space. For some embodiments, a multi-bit device ID, which corresponds to a memory segment to which that device is mapped, is loaded for each memory device. Higher order address bits are then compared to the device IDs assigned to each device. An internally generated chip select line is asserted for a device having a match between the address bits and its device ID.

Abstract: Receiving a request for canceling setting, a control circuit erases data stored in a corresponding block, changes a value of a protection flag, and cancels protection setting. When an overall protection is set for any block, the control circuit prohibits access to all blocks, except when it is an operation mode for activating a memory program contained in the microcomputer. Further, control circuit permits an access to a block M only when partial protection is set, CPU is in the mode for activating a memory program contained in the microcomputer and the access is for reading an instruction code in accordance with an instruction fetch.

Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Abstract: A digital data file storage system is disclosed in which original data files to be stored are dispersed using some form of information dispersal algorithm into a number of file “slices” or subsets in such a manner that the data in each file share is less usable or less recognizable or completely unusable or completely unrecognizable by itself except when combined with some or all of the other file shares. These file shares are stored on separate digital data storage devices as a way of increasing privacy and security. As dispersed file shares are being transferred to or stored on a grid of distributed storage locations, various grid resources may become non-operational or may operate below at a less than optimal level. When dispersed file shares are being written to a dispersed storage grid which not available, the grid clients designates the dispersed data shares that could not be written at that time on a Rebuild List.

Abstract: Provided are a method, system, and article of manufacture, where a plurality of extents are stored in a first set of storage units coupled to a controller. A determination is made that a second set of storage units has been coupled to the controller. The plurality of extents are distributed among all storage units included in the first set of storage units and the second set of storage units.

Abstract: A cache coherency technique used in a multi-node symmetric multi-processor system that reduces the number of message phases of a read request from 5 to 4, canceling the combined response phase for read requests in most cases, thereby improving system performance and reducing the overall system power consumption.

Abstract: Exemplary methods, systems, and products are described that operate generally by moving subroutine return address protection to the processor itself, in effect proving atomic locks for subroutine return addresses stored in a stack, subject to application control. More particularly, exemplary methods, systems, and products are described that write protect subroutine return addresses by calling a subroutine, including storing in a stack memory address a subroutine return address and locking, by a computer processor, the stack memory address against write access. Calling a subroutine may include receiving in the computer processor an instruction to lock the stack memory address. Locking the stack memory address may be carried out by storing the stack memory address in a protected memory lockword. A protected memory lockword may be implemented as a portion of a protected content addressable memory.

Abstract: In an embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory configured to store translation data; and control logic coupled to the memory and configured to translate an I/O device-generated memory request using the translation data. The translation data corresponds to one or more device table entries in a device table stored in a memory system of a computer system that includes the IOMMU, wherein the device table entry for a given request is selected by an identifier corresponding to the I/O device that generates the request. The translation data further corresponds to one or more I/O page tables, wherein the selected device table entry for the given request includes a pointer to a set of I/O page tables to be used to translate the given request.

Abstract: A page table mechanism translates virtual addresses to real addresses. In a first aspect, page table entries are contained in equal-sized blocks, the entries within each block corresponding to contiguous pages of virtual address space. Preferably, the common high-order portion of the virtual address is contained in segments distributed among multiple page table entries of the block. In a second aspect, the virtual address indexes a binary tree definitional structure. Decode logic traverses a binary tree defined by the definitional structure by testing selective bits of the virtual address to reach a leaf of the binary tree, which defines the location of data defining the real address.

Abstract: Embodiments of the present invention are directed to a scheme in which information as to the future behavior of particular software is used in order to optimize cache management and reduce cache pollution. Accordingly, a certain type of data can be defined as “short life data” by using knowledge of the expected behavior of particular software. Short life data can be a type of data which, according to the ordinary expected operation of the software, is not expected to be used by the software often in the future. Data blocks which are to be stored in the cache can be examined to determine if they are short life data blocks. If the data blocks are in fact short life data blocks they can be stored only in a particular short life area of the cache.

Abstract: The present disclosure provides embodiments of tape drive systems and methods. Briefly described, in architecture, one embodiment of a tape drive apparatus includes an interface for receiving a media access request and a unique identifier of a requestor. The tape drive apparatus also includes a data transfer apparatus for transferring data between a loaded tape cartridge and the tape drive apparatus. The data transfer apparatus is adapted to write a log entry to a log stored in a non-volatile memory of the tape cartridge, where the log entry includes at least the unique identifier. Other systems and methods are also provided.

Abstract: To enhance capacity expansion property of a storage system for providing a thin provisioning volume, this invention provides a computer system including: a first storage system; and a second storage system for providing a second volume to the first storage system. The first storage system is configured to: define at least one first volumes; define a first storage pool including the defined first volume and the provided second volume; provide to the host computer a first thin provisioning volume that is recognized as a volume having a capacity equal to or larger than that of storage areas assigned from the first storage pool. The first thin provisioning volume is thus assigned with both storage areas of the first volume and storage areas of the second volume, which are included in the first storage pool.

Abstract: The storage system includes a disk controller for receiving write commands from a computer, and a plurality of disk devices in which data is written in accordance with the control of the disk controller. The size of the first block which constitutes the data unit handled in the execution of the input/output processing of the data in accordance with the write command by the disk controller is different from the size of the second block which constitutes the data unit handled in the execution of the input/output processing of data by the plurality of disk devices. The disk controller issues an instruction for the writing of data to the disk devices using a third block unit of a size corresponding to a common multiple of the size of the first block and the size of the second block.

Abstract: A system for authenticating a memory card including: a memory card host device including a plural area authentication module which judges whether the memory card has plural storage areas, and an area switching module which switches a storage area subject to access a different storage area from among plural storage areas; a memory card including plural storage areas, at least one internal register which retains a value indicating the number of storage areas, and a controller which transmits the value indicating the number of the storage areas to the memory card host device; and a bus which transmits and receives data between the memory card host device and the memory card.