Patents Examined by Jack Lane
  • Patent number: 7958318
    Abstract: A second-level cache device stores part of registration information of data for a first-level cache device in a second-level cache-tag unit in association with registration information in a second-level-cache data unit, and stores the registration information of data for the first-level cache device in a first-level cache-tag copying unit. A coherency maintaining processor maintains coherency between the first-level cache device and the second-level cache device based on the information stored in the second-level cache-tag unit and the first-level cache-tag copying unit.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: June 7, 2011
    Assignee: Fujitsu Limited
    Inventors: Hideki Sakata, Hiroyuki Kojima, Masaki Ukai
  • Patent number: 7953924
    Abstract: A method for managing a plurality of servers is disclosed. Each server of the plurality of servers has access to data stored by other servers. The data is stored to one or more data storage devices. Coordinating information is written for the plurality of servers to a master mailbox record. The coordinating information includes data that each server uses to recover after a failure by a server. The master mailbox record is stored on a selected storage device at a location known to the plurality of servers, and the selected storage device is designated as a lock storage device. A plurality of lock storage devices is chosen so that in the event of failure of a server of the plurality of servers, at least one lock storage device will be available to the remaining servers.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: May 31, 2011
    Assignee: NetApp, Inc.
    Inventors: Richard O. Larson, Alan L. Rowe, Joydeep sen Sarma
  • Patent number: 7949843
    Abstract: A method for operating a computer data storage system is disclosed. The system operates an active file system on a first volume of a plurality of volumes of storage devices connected to one or more servers, each volume being a plurality of storage devices. Snapshots of the active file system are stored on one or more destination volumes. A mirroring operation is initiated on a selected server of the one or more servers. A scanner executes on the selected server, the scanner identifying a latest snapshot on each of the one or more destination volumes, the scanner. Data blocks which are newer than a latest snapshot stored at each destination volume are sent to each destination volume.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: May 24, 2011
    Assignee: NetApp, Inc.
    Inventor: Tianyu Jiang
  • Patent number: 7949820
    Abstract: In a system for reading and writing data, the system including a controller, multiple microprocessor units accessible to the controller, and multiple memory device configurations, each having one dedicated bus connection to individual ones or multiples of the microprocessor units, a method for managing access to one or more of the memory device configurations includes the steps, (a) receiving a request at the controller requiring access of at least one of the memory device configurations, (b) determining at the controller, which microprocessor unit or units will handle the request, (c) handing the request to the selected microprocessor unit or units, (d) determining at the microprocessor unit or units, the tasks specified in the request for that microprocessor unit or units and (e) determining a memory address or addresses in one or more of the memory device configurations and accessing the memory device configuration or configurations to satisfy the request.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: May 24, 2011
    Assignee: DataRam, Inc.
    Inventor: Jason Caulkins
  • Patent number: 7945754
    Abstract: A multiprocessor system includes processors each having a primary cache and a secondary cache shared by the processors. The processors each include a read unit that reads data from the primary cache, a request unit that makes a write request when the data to be read is not stored in the primary cache, a measuring unit that measures an elapsed time since the write request is made, a receiving unit that receives a read command from an external device, a comparing unit that compares specific information for specifying data, for which the read command has been received, with specific information for specifying data, for which the write request has been made, and a controller that suspends reading of the data according to the read command, when pieces of specific information are the same, and the elapsed time measured is less than a predetermined time.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: May 17, 2011
    Assignee: Fujitsu Limited
    Inventor: Naohiro Kiyota
  • Patent number: 7941600
    Abstract: The storage system includes a disk controller for receiving write commands from a computer, and a plurality of disk devices in which data is written in accordance with the control of the disk controller. The size of the first block which constitutes the data unit handled in the execution of the input/output processing of the data in accordance with the write command by the disk controller is different from the size of the second block which constitutes the data unit handled in the execution of the input/output processing of data by the plurality of disk devices. The disk controller issues an instruction for the writing of data to the disk devices using a third block unit of a size corresponding to a common multiple of the size of the first block and the size of the second block.
    Type: Grant
    Filed: August 3, 2010
    Date of Patent: May 10, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Ikuya Yagisawa, Naoto Matsunami
  • Patent number: 7941627
    Abstract: An instruction set architecture (ISA) includes an asynchronous memory move (AMM) synchronization (SYNC) instruction. When processor of a data processing system executes the AMM SYNC instruction, the processor prevents an AMM operation generated by a subsequently received/executed AMM ST instruction from proceeding with the data move portion of the AMM operation within the memory subsystem until completion of all ongoing memory access operations within the memory subsystem and fabric. The AMM operation does not wait for a normal barrier operation. The processor forwards the information relevant to initiate the AMM operation to an asynchronous memory mover logic, and signals the logic to not proceed with the AMM operation until signaled of the completion of the AMM SYNC.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Robert S. Blackmore, Chulho Kim, Balaram Sinharoy, Hanhong Xue
  • Patent number: 7937548
    Abstract: A system and method of creating a snapclone for on-line point-in-time complete backup in a virtualized storage system is disclosed. In one embodiment, a method for creating a snapclone for on-line point-in-time complete backup in a virtualized storage system includes receiving a copy operation directed to one or more identified segments of an original virtual disk, in response to the copy operation, substantially sequentially copying the one or more identified segments to a snapclone virtual disk, clearing bits in an in-memory sharing bitmap associated with already copied one or more identified segments, and writing the cleared bits in the in-memory sharing bitmap to a disk resident virtual disk metadata associated with the snapclone virtual disk upon receiving a current write I/O operation while the copy operation is in progress. The received current write I/O operation is targeting data outside the LBA range of the already copied one or more identified segments.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: May 3, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Kishore Kaniyar Sampathkumar
  • Patent number: 7930468
    Abstract: A system for writing and reading data includes a controller accessible to at least one or more computing systems, a plurality of microprocessor units accessible to the controller, and a plurality of memory device configurations each having one dedicated bus connection to individual ones or multiples of the microprocessor units. The controller receives write and read requests from the one or more computing systems and selects which of the plurality of microprocessor units will write or read data associated with the requests.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: April 19, 2011
    Assignee: Dataram, Inc.
    Inventor: Jason Caulkins
  • Patent number: 7917726
    Abstract: In one embodiment, an input/output (I/O) memory management unit (IOMMU) comprises at least one memory and control logic coupled to the memory. The memory is configured to store translation data corresponding to one or more I/O translation tables stored in a memory system of a computer system that includes the IOMMU. The control logic is configured to translate an I/O device-generated memory request using the translation data. The translation data includes a type field indicating one or more attributes of the translation, and the control logic is configured to control the translation responsive to the type field.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: March 29, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark D. Hummel, Geoffrey S. Strongin, Andrew W. Lueck
  • Patent number: 7913033
    Abstract: Memory devices and methods disclosed such as memory devices that include a network identification that uniquely identifies the memory device on a network. The memory device can then receive memory commands that include the network identification. The memory device can also generate memory commands, including the network identification, for broadcast over the network.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: March 22, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 7913030
    Abstract: In one aspect, a system for indexing transactions over a shared bus is described. In various embodiments, the system includes a host controller and a plurality of storage devices in communication with the bus. Each of the storage devices is configured to store data. The bus facilitates communications between the host controller and the plurality of storage devices. A selected one of the storage devices is configured to function as a transaction indexer to monitor the bus and index and store selected transaction information associated with operations that occur over the bus. While the host controller may be arranged to configure the transaction indexer, the transaction monitoring, indexing and storing are performed substantially automatically by the transaction indexer without requiring further instructions from the host controller.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: March 22, 2011
    Assignee: SanDisk IL Ltd.
    Inventors: Nir Perry, Polina Marimont, Alain Nochimowski
  • Patent number: 7913029
    Abstract: According to one embodiment, an information recording apparatus has a control unit configured to control mutual transfer of information between each of a disc-shaped recording medium, a cache memory, and a non-volatile memory and the outside, control mutual transfer of information between the disc-shaped recording medium, the cache memory, and the non-volatile memory, and control to set a substituting region corresponding to a defect region generated in the disc-shaped recording medium in the non-volatile memory.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kenji Yoshida
  • Patent number: 7907470
    Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: March 15, 2011
    Assignee: RAMBUS Inc.
    Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
  • Patent number: 7908456
    Abstract: Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods and systems manage transactional memory operations by using identifiers, such as sequence numbers, to handle memory management in transactions. The methods and systems also maintain lists of deferred actions to be performed at transaction abort and commit times. A number of memory management routines associated with one or more transactions examine the transaction sequence number of the current transaction, manipulate commit and/or undo logs, and set/use the transaction sequence number of an associated object, but are not so limited. The methods and systems provide for memory allocation and deallocations within transactional code while preserving transactional semantics. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: March 15, 2011
    Assignee: Intel Corporation
    Inventors: Ben Hertzberg, Bratin Saha, Ali-Reza Adi-Tabatabai
  • Patent number: 7904693
    Abstract: An addressing model is provided where devices, including I/O devices, are addressed with internet protocol (IP) addresses, which are considered part of the virtual address space. A task, such as an application, may be assigned an effective address range, which corresponds to addresses in the virtual address space. The virtual address space is expanded to include Internet protocol addresses. Thus, the page frame tables are also modified to include entries for IP addresses and additional properties for devices and I/O. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: March 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Claude Basso, Jean L. Calvignac, Piyush Chaudhary, Edward J. Seminaro
  • Patent number: 7899971
    Abstract: A storage controller of the present invention is capable of providing a plurality of external volumes to a mainframe as a single virtual volume without lowering write performance. A virtual volume inside a main storage apparatus is associated with a plurality of external volumes inside an external storage apparatus. When the mainframe formats the virtual volume, a control information creation unit of the main storage apparatus creates and stores control information related to the virtual volume. Consequently, it is possible to enhance processing performance when the write size specified by the mainframe coincides with the data size set in the write destination, that is, during a so-called isometric write.
    Type: Grant
    Filed: March 5, 2008
    Date of Patent: March 1, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Mori, Shinichi Hiramatsu
  • Patent number: 7900016
    Abstract: An addressing model is provided where all resources, including memory and devices, are addressed with internet protocol (IP) addresses. A task, such as an application, may be assigned a range of IP addresses rather than an effective address range. Thus, a processing element, such as an I/O adapter or even a printer, for example, may also be addressed using IP addresses without the need for library calls, device drivers, pinning memory, and so forth. This addressing model also provides full virtualization of resources across an IP interconnect, allowing a process to access an I/O device across a network.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ravi K. Arimilli, Claude Basso, Jean L. Calvignac, Piyush Chaudhary, Edward J. Seminaro
  • Patent number: 7900002
    Abstract: Backup and restore technology comprising a backup engine, one or more client backup modules coupled to the backup engine via a backup protocol, and a backup database coupled to the backup engine, the backup database including a set of clusters, the set of clusters forming one or more backups, wherein each cluster of the set of clusters is unique such that single-instance storage across clients is achieved.
    Type: Grant
    Filed: March 3, 2008
    Date of Patent: March 1, 2011
    Assignee: Microsoft Corporation
    Inventor: James M Lyon
  • Patent number: 7895409
    Abstract: An embodiment of the invention provides an apparatus and method for determining a security partition in a computer for an application. The apparatus and method can determine required system resources, security requirements, and partition rules for an application, can determine allocated system resources, security characteristics, and partitions rules for each security partition in the computer, and can identify at least one proposed security partition for the application.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: February 22, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: John J. Mendonca