Abstract: The present invention relates to a preparation method for a semiconductor material leg array and a batch preparation method for an interface layer of a semiconductor material leg array. The preparation method for a semiconductor material leg array comprises: placing a semiconductor block material on a surface of an extrusion mold, placing the semiconductor block material and the extrusion mold in a pressure-resistant sleeve, subjecting the semiconductor block material to plastic deformation by extrusion and filling holes that are arranged in an array on the surface of the extrusion mold, and demolding to obtain a semiconductor material leg array.

Abstract: A semiconductor device structure and method of manufacturing the same are provided. The semiconductor device structure includes a substrate, a first well region, a source/drain (S/D) feature, and a pick-up region. The substrate has a first surface and a second surface opposite to the first surface. The first well region abuts the second surface of the substrate and has a first conducive type. The S/D feature abuts the second surface of the substrate and has a second conductive type different from the first conductive type. The pick-up region abuts the first surface of the substrate and has the first conductive type.

Abstract: Provided is an organic light-emitting diode, wherein the organic light-emitting diode includes: a first electrode, at least two emission layers, an optical modulation layer and a second electrode which are sequentially laminated on a base substrate; wherein a color of a mixture of light emitted from the at least two emission layers is white; and a thickness of the optical modulation layer ranges from 5 nm to 100 nm.

Abstract: According to one embodiment, a nitride semiconductor includes a nitride member. The nitride member includes a first nitride region, and a second nitride region. The first nitride region includes Alx1Ga1-x1N (0?x1<1). The Alx1Ga1-x1N includes a first element. The first element includes at least one selected from the group consisting of Fe and Mn. The second nitride region includes Alx1Ga1-x1N (0?x1<1). A direction from the first nitride region to the second nitride region is along a first direction. A second lattice length of the second nitride region in a first axis crossing the first direction is different from a first lattice length of the first nitride region in the first axis.

Abstract: A manufacturing method for a semiconductor device including a first semiconductor element and a second semiconductor element, includes the steps of forming an insulating layer on a first substrate having a first elastic modulus higher than a second elastic modulus, forming a first semiconductor element having a first bonding surface on the insulating layer, forming a second semiconductor element having a second bonding surface on a second substrate having the second elastic modulus, bonding the first bonding surface and the second bonding surface to each other to form a laminate of the first semiconductor element and the second semiconductor element, and removing the first substrate from the laminate.

Abstract: A display device includes a display panel including a pressed area, a non-pressed area, and an alignment mark area defined on a rear surface overlapping the pressed area, a driving chip disposed on a front surface of the display panel overlapping the pressed area, and a cover panel disposed on the rear surface of the display panel. The cover panel includes a first functional layer disposed on the rear surface of the display panel overlapping the non-pressed area, a second functional layer disposed on the first functional layer, extending along the first functional layer, and disposed on the rear surface of the display panel overlapping the pressed area, and a third functional layer disposed on the second functional layer overlapping the pressed area.

Abstract: Structural thermal interfacing for lidded semiconductor packages, including: applying, to a periphery of a surface of a chip, a stiffening adhesive framing a center portion of the chip; applying, to the center portion of the chip, a thermal interface material; and applying a lid to the chip, wherein the lid contacts the stiffening adhesive and is thermally coupled to the chip via the thermal interface material after application to the chip.

Abstract: In one example, an electronic device comprises a base, a substrate over the base and comprising a top side, a bottom side, and a conductive structure, wherein the substrate further comprises a channel opening and an aperture, and wherein the bottom side of the substrate is oriented toward the base, an electronic component over the top side of the substrate and over the aperture, wherein the electronic component is coupled with the conductive structure, and a funnel over the top side of the substrate and comprising a funnel opening. A top side of the electronic component is exposed through the funnel opening. Other examples and related methods are also disclosed herein.

Abstract: The present disclosure relates methods, devices, systems, and techniques for merging schemes in semiconductor devices such as three-dimensional (3D) semiconductor devices. In one aspect, a semiconductor device includes a semiconductor structure that includes a stack of conductive layers and insulating layers alternating with each other along a first direction. The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The semiconductor device further includes multiple contact structures extending through the connection region along the first direction. Each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure of the multiple contact structures and isolated from one or more other contact structures of the multiple contact structures.

Abstract: A semiconductor device includes a first electrode, a plurality of unit element regions, and a partitioning region. Each of the unit element regions includes a first semiconductor part, a second electrode, and a first conductive part. The first semiconductor part includes first to third semiconductor regions. The first semiconductor region is located above the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The second electrode is located on the second and third semiconductor regions. The first conductive part faces the second semiconductor region via a first insulating film. At least a portion of the plurality of unit element regions includes a common pattern. The partitioning region includes a second semiconductor part and partitions the plurality of unit element regions. The second semiconductor part is continuous with the first semiconductor part.

Abstract: In described examples, a first device on a first surface of a substrate is coupled to a structure arranged on a second surface of the substrate. In at least one example, a first conductor arranged on the first surface is coupled to circuitry of the first device. An elevated portion of the first conductor is supported by disposing an encapsulate and curing the encapsulate. The first conductor is severed by cutting the encapsulate and the first conductor. A second conductor is coupled to the first conductor. The second conductor is coupled to the structure arranged on the second surface of the substrate.

Abstract: An integrated circuit includes first semiconductor regions each having a silicided portion with group-III, group-IV, and/or group-V atoms implanted therein. In each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is maximum at an interface between the silicided portion and a non-silicided portion. Other semiconductor regions in the integrated circuit each include a silicided portion also having group-III, group-IV, and/or group-V atoms implanted therein. The silicided portions of the first semiconductor regions are thicker than the silicided portions of the other semiconductor regions. The group-III, group-IV, and/or group-V atoms of the first semiconductor regions and of the other semiconductor regions may be carbon and/or germanium atoms.

Abstract: In a field effect transistor, trench lower layers are disposed directly below corresponding trenches. Deep layers of p-type extend along a first direction intersecting the trenches and are arranged at intervals along a second direction orthogonal to the first direction. A drain-side layer of n-type is distributed from a position in contact with a lower surface of a body layer to a position below a lower end of each of the deep layers through intervals between the deep layers. The drain-side layer includes a high concentration layer distributed in at least a part of a depth range in which both the deep layers and the trench lower layers are present, and an intermediate concentration layer distributed in at least a part of a depth range between a lower end of the high concentration layer and a lower end of each of the deep layers.

Abstract: A microelectronic device includes a hybrid component. The microelectronic device has a substrate including silicon semiconductor material. The hybrid component includes a silicon portion in the silicon, and a wide bandgap (WBG) structure on the silicon. The WBG structure includes a WBG semiconductor material having a bandgap energy greater than a bandgap energy of the silicon. The hybrid component has a first current terminal on the silicon, and a second current terminal on the WBG structure. The microelectronic device may be formed by forming the silicon portion of the hybrid component in the silicon, and subsequently forming the WBG structure in a silicon recess on the silicon.

Abstract: The present invention discloses an equivalent source and drain region optimized field-effect transistor device for solving the problem of short-channel effects of a field-effect transistor in the prior art. The field-effect transistor device includes an active layer, and the active layer includes a source region, a drain region and a channel region located between the source region and the drain region; when the device is on, an effective channel and an equivalent source region and an equivalent drain region away from the effective channel at least in the thickness direction of the channel region are formed in the channel region, and the field-effect transistor device communicates the source region and the drain region via the effective channel and the equivalent source region and the equivalent drain region to contribute a working current, wherein the length of the equivalent source region is greater than that of the equivalent drain region.

Abstract: Methods, a display system and projection screen are described. The projection screen includes a substrate supporting a plurality of pixels. Each pixel has a sensitizing part communicating with at least one light source, the sensitizing part being configured to detect a presence of a non-visible medium indicative of a part of an image, and to activate the at least one light source to emit light. The pixels having a first electrode and a second electrode configured to supply electricity to the sensitizing part and the light source.

Abstract: A semiconductor element includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first intermediate layer, a second intermediate layer, a source electrode, a drain electrode, and a gate electrode. The band gap of the second semiconductor layer is larger than the band gaps of the first semiconductor layer and the third semiconductor layer. The band gaps of the first intermediate layer and the second intermediate layer that sandwich the second semiconductor layer are larger than the band gap of the second semiconductor layer.

Abstract: A method of fabricating a power semiconductor device includes forming a bi layer mask on a semiconductor substrate, where the bilayer mask comprises a first dielectric layer on the semiconductor substrate and a second dielectric layer on the first dielectric layer. The first and second dielectric layers are through-etched to define an exposed portion of the semiconductor substrate. The first dielectric layer is selectively etched to form an undercut region of the bi layer mask. A crystalline semiconductor material is epitaxially grown on the exposed portion of the semiconductor substrate, and a polycrystalline semiconductor material is deposited on the second dielectric layer of the bilayer mask. After the epitaxial growth, the bilayer mask and the polycrystalline semiconductor material are removed from the semiconductor substrate, leaving behind a mesa comprising the crystalline semiconductor material on the semiconductor substrate.

Abstract: Methods provided herein may include illuminating a region on a wafer within a semiconductor processing tool, the wafer having a layer of a material that is at least semi-transparent to light and has a measurable extinction coefficient, and the region being a first fraction of the wafer's surface, detecting light reflected off the material and off a surface underneath the material using one or more detectors and generating optical data corresponding to the detected light, generating a metric associated with a property of the material on the wafer by applying the optical data to a transfer function that relates the optical data to the metric associated with the property of the material on the wafer, determining an adjustment to one or more processing parameters for a processing module, and performing or modifying a processing operation in the processing module according to the adjusted one or more processing parameters.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a channel layer on the substrate, a first barrier layer on the channel layer, a second barrier layer on the first barrier layer, and a gate element on the second barrier layer. The first barrier layer includes a first material with a first band gap, the second barrier layer includes a second material with a second band gap, and the first band gap is greater than the second band gap.