Abstract: A method of forming a ruthenium film on a substrate by supplying a ruthenium-containing gas includes: forming an adsorption inhibition layer that inhibits adsorption of the ruthenium-containing gas by supplying an adsorption inhibition gas to an end portion and a rear surface of the substrate; transferring the substrate to a chamber; and forming the ruthenium film on the substrate by supplying the ruthenium-containing gas to the chamber.

Abstract: A display panel includes a display substrate and a touch layer. The display substrate includes a substrate and an anode layer. The anode layer includes a plurality of anodes, and at least one edge of at least one anode is provided with at least one groove therein. The touch layer is located on a light exit side of the display substrate. The touch layer includes a metal mesh structure, the metal mesh structure includes a plurality of first metal lines, and each first metal line includes an opening. An orthographic projection of each of the plurality of first metal lines on the substrate is located between orthographic projections of the plurality of anodes on the substrate. An orthogonal projection of each groove of the at least one anode on the substrate is disposed opposite to an orthogonal projection of an opening of a first metal line on the substrate.

Abstract: A vertical oriented semiconductor device is provided. The present disclosure further provides that at least one of the well regions of the device have at least two lateral doping gradients, at different depths in the semiconductor material, and each doping gradient has a monotonic decreasing doping concentration, from a higher doping concentration at a first lateral end of the well regions towards a lower doping concentration at a second, opposite lateral end thereof facing the current-accommodating region. These two doping gradients, at different depths, differ from each other, with one of the advantages being that the semiconductor device is made more robust. Multiple ways of implementing the two different lateral doping gradients are provided. Some of the advantages are that the electric field crowding at the corners of the well regions is gradually reduced, and the current distribution can be improved.

Abstract: A light emitting element includes a first electrode, a second electrode facing the first electrode, and a plurality of light emitting structures stacked between the first electrode and the second electrode, each of the plurality of light emitting structures including a hole transport region, a light emitting layer, and an electron transport region. At least one of the light emitting structures is a green light emitting structure which emits green light, and the light emitting layer of the green light emitting structure includes a first sub-light emitting layer including a low refractive material having a refractive index value less than or equal to about 1.7 at 460 nm, and a second sub-light emitting layer not including the low refractive material, and disposed on the first sub-light emitting layer, so that the light emitting element may exhibit high light emission efficiency.

Abstract: A semiconductor package with a heat dissipation interface has a substrate, at least one die embedded in the substrate, an insulation layer encompassing the die and covering the substrate, an upper redistribution layer (RDL) and a lower RDL respectively formed on opposite sides of the substrate, wherein an insulated adhesive comprehensively covers the lower RDL, and a dissipation layer is further bonded on the insulated adhesive. The dissipation layer evenly dissipates excessive heat energy generated by the die, thereby improving the heat dissipation efficiency.

Abstract: A semiconductor device comprises a semiconductor body, a gate electrode and a first electrode, wherein the semiconductor body comprises a first region which is a source region or an emitter region, and comprises a well region, the first region is of a first conductivity type and the well region is of a different, second conductivity type, the well region is separated from the gate electrode by a gate insulator layer, the first region is electrically contacted by means of the first electrode which is a source electrode or an emitter electrode, in the first region there is at least one current limiting region, and the at least one current limiting region is of at least one electrically insulating material.

Abstract: According to one embodiment, a semiconductor device includes a first transistor, and a first mounting member. The first transistor includes a nitride semiconductor layer and includes a first element electrode, a second element electrode, and a third element electrode. The first mounting member includes a first frame electrode, a plurality of first frame connection members electrically connecting the first element electrode and the first frame electrode, a first pad electrode, and a first pad connection member electrically connecting the first element electrode and the first pad electrode.

Abstract: The present invention relates to a preparation method for a semiconductor material leg array and a batch preparation method for an interface layer of a semiconductor material leg array. The preparation method for a semiconductor material leg array comprises: placing a semiconductor block material on a surface of an extrusion mold, placing the semiconductor block material and the extrusion mold in a pressure-resistant sleeve, subjecting the semiconductor block material to plastic deformation by extrusion and filling holes that are arranged in an array on the surface of the extrusion mold, and demolding to obtain a semiconductor material leg array.

Abstract: A semiconductor device structure and method of manufacturing the same are provided. The semiconductor device structure includes a substrate, a first well region, a source/drain (S/D) feature, and a pick-up region. The substrate has a first surface and a second surface opposite to the first surface. The first well region abuts the second surface of the substrate and has a first conducive type. The S/D feature abuts the second surface of the substrate and has a second conductive type different from the first conductive type. The pick-up region abuts the first surface of the substrate and has the first conductive type.

Abstract: Provided is an organic light-emitting diode, wherein the organic light-emitting diode includes: a first electrode, at least two emission layers, an optical modulation layer and a second electrode which are sequentially laminated on a base substrate; wherein a color of a mixture of light emitted from the at least two emission layers is white; and a thickness of the optical modulation layer ranges from 5 nm to 100 nm.

Abstract: According to one embodiment, a nitride semiconductor includes a nitride member. The nitride member includes a first nitride region, and a second nitride region. The first nitride region includes Alx1Ga1-x1N (0?x1<1). The Alx1Ga1-x1N includes a first element. The first element includes at least one selected from the group consisting of Fe and Mn. The second nitride region includes Alx1Ga1-x1N (0?x1<1). A direction from the first nitride region to the second nitride region is along a first direction. A second lattice length of the second nitride region in a first axis crossing the first direction is different from a first lattice length of the first nitride region in the first axis.

Abstract: A manufacturing method for a semiconductor device including a first semiconductor element and a second semiconductor element, includes the steps of forming an insulating layer on a first substrate having a first elastic modulus higher than a second elastic modulus, forming a first semiconductor element having a first bonding surface on the insulating layer, forming a second semiconductor element having a second bonding surface on a second substrate having the second elastic modulus, bonding the first bonding surface and the second bonding surface to each other to form a laminate of the first semiconductor element and the second semiconductor element, and removing the first substrate from the laminate.

Abstract: A display device includes a display panel including a pressed area, a non-pressed area, and an alignment mark area defined on a rear surface overlapping the pressed area, a driving chip disposed on a front surface of the display panel overlapping the pressed area, and a cover panel disposed on the rear surface of the display panel. The cover panel includes a first functional layer disposed on the rear surface of the display panel overlapping the non-pressed area, a second functional layer disposed on the first functional layer, extending along the first functional layer, and disposed on the rear surface of the display panel overlapping the pressed area, and a third functional layer disposed on the second functional layer overlapping the pressed area.

Abstract: Structural thermal interfacing for lidded semiconductor packages, including: applying, to a periphery of a surface of a chip, a stiffening adhesive framing a center portion of the chip; applying, to the center portion of the chip, a thermal interface material; and applying a lid to the chip, wherein the lid contacts the stiffening adhesive and is thermally coupled to the chip via the thermal interface material after application to the chip.

Abstract: In one example, an electronic device comprises a base, a substrate over the base and comprising a top side, a bottom side, and a conductive structure, wherein the substrate further comprises a channel opening and an aperture, and wherein the bottom side of the substrate is oriented toward the base, an electronic component over the top side of the substrate and over the aperture, wherein the electronic component is coupled with the conductive structure, and a funnel over the top side of the substrate and comprising a funnel opening. A top side of the electronic component is exposed through the funnel opening. Other examples and related methods are also disclosed herein.

Abstract: The present disclosure relates methods, devices, systems, and techniques for merging schemes in semiconductor devices such as three-dimensional (3D) semiconductor devices. In one aspect, a semiconductor device includes a semiconductor structure that includes a stack of conductive layers and insulating layers alternating with each other along a first direction. The semiconductor structure includes an array region and a connection region adjacent to the array region in a second direction perpendicular to the first direction. The semiconductor device further includes multiple contact structures extending through the connection region along the first direction. Each conductive layer in the stack of conductive layers and insulating layers is coupled to a corresponding contact structure of the multiple contact structures and isolated from one or more other contact structures of the multiple contact structures.

Abstract: A semiconductor device includes a first electrode, a plurality of unit element regions, and a partitioning region. Each of the unit element regions includes a first semiconductor part, a second electrode, and a first conductive part. The first semiconductor part includes first to third semiconductor regions. The first semiconductor region is located above the first electrode. The second semiconductor region is located on the first semiconductor region. The third semiconductor region is located on the second semiconductor region. The second electrode is located on the second and third semiconductor regions. The first conductive part faces the second semiconductor region via a first insulating film. At least a portion of the plurality of unit element regions includes a common pattern. The partitioning region includes a second semiconductor part and partitions the plurality of unit element regions. The second semiconductor part is continuous with the first semiconductor part.

Abstract: In described examples, a first device on a first surface of a substrate is coupled to a structure arranged on a second surface of the substrate. In at least one example, a first conductor arranged on the first surface is coupled to circuitry of the first device. An elevated portion of the first conductor is supported by disposing an encapsulate and curing the encapsulate. The first conductor is severed by cutting the encapsulate and the first conductor. A second conductor is coupled to the first conductor. The second conductor is coupled to the structure arranged on the second surface of the substrate.

Abstract: An integrated circuit includes first semiconductor regions each having a silicided portion with group-III, group-IV, and/or group-V atoms implanted therein. In each first semiconductor region, a concentration of the group-III, group-IV, and/or group-V atoms is maximum at an interface between the silicided portion and a non-silicided portion. Other semiconductor regions in the integrated circuit each include a silicided portion also having group-III, group-IV, and/or group-V atoms implanted therein. The silicided portions of the first semiconductor regions are thicker than the silicided portions of the other semiconductor regions. The group-III, group-IV, and/or group-V atoms of the first semiconductor regions and of the other semiconductor regions may be carbon and/or germanium atoms.

Abstract: In a field effect transistor, trench lower layers are disposed directly below corresponding trenches. Deep layers of p-type extend along a first direction intersecting the trenches and are arranged at intervals along a second direction orthogonal to the first direction. A drain-side layer of n-type is distributed from a position in contact with a lower surface of a body layer to a position below a lower end of each of the deep layers through intervals between the deep layers. The drain-side layer includes a high concentration layer distributed in at least a part of a depth range in which both the deep layers and the trench lower layers are present, and an intermediate concentration layer distributed in at least a part of a depth range between a lower end of the high concentration layer and a lower end of each of the deep layers.