Patents Examined by Jack S Chen
  • Patent number: 10886404
    Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Young Kim, Deok Han Bae, Byung Chan Ryu, Da Un Jeon
  • Patent number: 10879269
    Abstract: A ferroelectric memory unit cell includes a series connection of select gate transistor that turns the ferroelectric memory unit cell on and off, and a ferroelectric memory transistor. Data is stored in a ferroelectric material layer of the ferroelectric memory transistor. The ferroelectric memory unit cell may be a planar structure in which both transistors are planar transistors with horizontal current directions. In this case, the gate electrode of the access transistor can be formed as a buried conductive line. Alternatively, the ferroelectric memory unit cell may include a vertical stack of vertical semiconductor channels.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier
  • Patent number: 10879126
    Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shahaji B. More, Zheng-Yang Pan, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 10879321
    Abstract: A display device includes: a first substrate including a display region and a non-display region provided at at least one side of the display region; a plurality of pixel units provided in the display region on the first substrate; a metal pattern provided in the non-display region on the first substrate; and a second substrate opposite to the first substrate, the second substrate being joined with the first substrate to encapsulate the display region, wherein the metal pattern includes a material having a high reactivity with oxygen as compared with an organic material.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sung Hoon Song
  • Patent number: 10867797
    Abstract: The wafer fabrication technique uses an ion implantation process on the back side of the wafer to control the shape of the wafer. At least one first dopant is implanted into a front side of a wafer to dope the wafer. At least one second dopant is implanted into a back side of the wafer in a dopant profile to create a back side structure, where the back side structure controls a shape of the wafer. A blank wafer is provided that has an undoped front side and a form shaping back side structure on the back side. A doped wafer is provided that has a dopant implanted on the front side and a form shaping back side structure on the back side that least partially offsets the strain in the wafer induced by the front side dopant.
    Type: Grant
    Filed: February 7, 2019
    Date of Patent: December 15, 2020
    Assignee: Cree, Inc.
    Inventors: Alexander Suvorov, Robert Leonard, Edward Robert Van Brunt
  • Patent number: 10854520
    Abstract: The present invention provides a method for forming a semiconductor structure. The method including: Firstly, a substrate is provided, a first region and a second region are defined thereon, next, a gate dielectric layer and a work function metal layer are sequentially formed on the substrate within the first region and within the second region. Afterwards, a dielectric layer is formed on the work function metal layer within the second region, a hydrogen gas treatment is then performed on the substrate, and the work function metal layer is removed within the first region.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Lin Lu, Chun-Lung Chen, Kun-Yuan Liao, Chun-Hsien Lin, Wei-Hao Huang, Kai-Teng Cheng
  • Patent number: 10854504
    Abstract: The present disclosure provides a semiconductor structure having a semiconductor layer; a gate with a conductive portion and a sidewall spacer; an interlayer dielectric (ILD) surrounding the sidewall spacer; and a nitrogen-containing protection layer, positioning at least on the top surface of the conductive portion of the gate. A top surface of the conductive portion and a top surface of the sidewall spacer are substantially coplanar. The nitrogen-containing protection layer is not covering the sidewall surface of the sidewall spacer. The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a metal gate structure having a conductive portion and a sidewall spacer surrounded by a first ILD; forming a protection layer over the metal gate structure, and the protection layer is formed to cover at least the conductive portion of the metal gate structure; and forming a second ILD over the metal gate structure.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Jr-Jung Lin, Chih-Han Lin, Yung Jung Chang
  • Patent number: 10832986
    Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip disposed in the through-hole and including an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, a second connection member disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the semiconductor chip, and an encapsulant encapsulating the semiconductor chip and having a cavity disposed above the inactive surface of the semiconductor chip.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Hyun Cho, Young Sik Hur, Yong Ho Baek
  • Patent number: 10833163
    Abstract: The present invention provides an epitaxial structure of N-face group III nitride, its active device, and the method for fabricating the same. By using a fluorine-ion structure in device design, a 2DEG in the epitaxial structure of N-face group III nitride below the fluorine-ion structure will be depleted. Then the 2DEG is located at a junction between a i-GaN channel layer and a i-AlyGaN layer, and thus fabricating GaN enhancement-mode AlGaN/GaN high electron mobility transistors (HEMTs), hybrid Schottky barrier diodes (SBDs), or hybrid devices. After the fabrication step for polarity inversion, namely, generating stress in a passivation dielectric layer, the 2DEG will be raised from the junction between the i-GaN channel layer and the i-AlyGaN layer to the junction between the i-GaN channel layer and the i-AlxGaN layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: November 10, 2020
    Inventor: Chih-Shu Huang
  • Patent number: 10826019
    Abstract: A display device includes: a plurality of organic layers each made of an organic material and each having a predetermined modulus of elasticity and a predetermined thickness; and a plurality of inorganic layers each made of an inorganic material and each having a predetermined modulus of elasticity and a predetermined thickness. The plurality of organic layers and the plurality of inorganic layers are stacked together to constitute a device body which forms the display device. A quotient obtained by dividing the sum of flexural rigidities of the plurality of inorganic layers by the sum total of the sum of flexural rigidities of the plurality of organic layers and the sum of the flexural rigidities of the plurality of inorganic layers is 0.78 or higher and 1 or lower.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: November 3, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takashi Ochi, Mamoru Ishida, Tohru Sonoda, Tohru Senoo, Takeshi Hirase
  • Patent number: 10825949
    Abstract: Provided is a method of manufacturing a light emitting device, comprising: preparing a base body having a concave portion; disposing a light emitting element at the bottom of the concave portion; disposing a first resin containing first phosphor particles having an average particle size of 10 ?m or more and 30 ?m or less and a first filler having an average particle size of 5 ?m or more and 20 ?m or less to cover the light emitting element; centrifugally precipitating the first phosphor particles and the first filler toward the base body; temporarily curing the first resin; disposing a second resin containing second phosphor particles and a second filler having an average particle size of 5 nm or more and 100 nm or less on the first resin temporarily cured; centrifugally precipitating the second phosphor particles and the second filler toward the first resin; and curing the first and second resins.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 3, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Makoto Nakano, Kenji Nakata
  • Patent number: 10811493
    Abstract: Examples described herein provide for single event latch-up (SEL) mitigation techniques. In an example, a semiconductor structure includes a semiconductor substrate, a p-type transistor having p+ source/drain regions disposed in a n-doped region in the semiconductor substrate, an n-type transistor having n+ source/drain regions disposed in a p-doped region in the semiconductor substrate, a n+ guard ring disposed in the n-doped region and laterally around the p+ source/drain regions of the p-type transistor, and a p+ guard ring disposed laterally around the n-doped region. The p+ guard ring is disposed between the p-type transistor and the n-type transistor.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: October 20, 2020
    Assignee: XILINX, INC.
    Inventors: James Karp, Michael J. Hart
  • Patent number: 10811431
    Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 20, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Yanli Zhang
  • Patent number: 10804376
    Abstract: A method of manufacturing a semiconductor device includes preparing a first wafer including a first trench; forming a first semiconductor layer inside the first trench so that a first space remains in the first trench; obtaining a first level corresponding to a bottom of the first space and a second level estimated by a size or a shape of the first space; preparing a second wafer including a second trench having a shape and a size substantially same as a shape and a size of the first trench; forming a second semiconductor layer inside the second trench in the second so that a second space remains in the second trench; forming a third semiconductor layer to fill the second space in the second trench; and removing a surface portion of the second wafer to a depth corresponding to a level between the first level and the second level.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: October 13, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Shigeaki Takagi
  • Patent number: 10794948
    Abstract: An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekaran Kothandaraman, John M. Safran, Timothy D. Sullivan, Ping-Chuan Wang, Lijuan Zhang
  • Patent number: 10797239
    Abstract: A method for forming a semiconductor device is disclosed. The method for forming the semiconductor device includes forming a first sacrificial film over a target layer to be etched, forming a first partition mask over the first sacrificial film, forming a first sacrificial film pattern by etching the first sacrificial film using the first partition mask, forming a first spacer at a sidewall of the first sacrificial film pattern, and forming a first spacer pattern by removing the first sacrificial film pattern. The first partition mask includes a plurality of first line-shaped space patterns extending in a first direction. A width of at least one space pattern located at both edges from among the plurality of first space patterns is smaller than a width of each of other space patterns.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: October 6, 2020
    Assignee: SK hynix Inc.
    Inventors: Joo Young Moon, Young Seok Ko, Soo Gil Kim
  • Patent number: 10797145
    Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: October 6, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura, Katsuhisa Nagao
  • Patent number: 10790314
    Abstract: A display panel and a display device comprising the same are provided. The display panel includes a planar substrate and a boundary substrate formed by bending the boundary of the planar substrate; and scan lines arranged on the planar substrate and extended to the boundary substrate. The width of the scan line on the bended position of the planar substrate is larger than the width of the remaining scan line.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 29, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Guowei Zha
  • Patent number: 10784181
    Abstract: An apparatus includes a circuit device, a heat sink fin, and a thermal interface material layer. The thermal interface material layer is thermally coupled to the circuit device and the heat sink fin. The thermal interface material layer includes a first alloy layer, a nanometal particle layer, and a second alloy layer. The first alloy layer is thermally coupled to the circuit device. The nanometal particle layer is thermally coupled to the first alloy layer. The nanometal particle layer includes nanometal particles and an intermediate mixture.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: September 22, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: HuiLi Fu, Jyh Rong Lin, Shujie Cai
  • Patent number: 10784375
    Abstract: A device including a gate stack over a semiconductor substrate having a pair of spacers abutting sidewalls of the gate stack. A recess is formed in the semiconductor substrate adjacent the gate stack. The recess has a first profile having substantially vertical sidewalls and a second profile contiguous with and below the first profile. The first and second profiles provide a bottle-neck shaped profile of the recess in the semiconductor substrate, the second profile having a greater width within the semiconductor substrate than the first profile. The recess is filled with a semiconductor material. A pair of spacers are disposed overly the semiconductor substrate adjacent the recess.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Eric Peng, Chao-Cheng Chen, Chii-Horng Li, Ming-Hua Yu, Shih-Hao Lo, Syun-Ming Jang, Tze-Liang Lee, Ying Hao Hsieh