Patents Examined by Jack S Chen
  • Patent number: 11901195
    Abstract: Aspects of the present disclosure relate to methods, systems, and apparatus for conducting a radical treatment operation on a substrate prior to conducting an annealing operation on the substrate. In one implementation, a method of processing semiconductor substrates includes pre-heating a substrate, and exposing the substrate to species radicals. The exposing of the substrate to the species radicals includes a treatment temperature that is less than 300 degrees Celsius, a treatment pressure that is less than 1.0 Torr, and a treatment time that is within a range of 8.0 minutes to 12.0 minutes. The method includes annealing the substrate after the exposing of the substrate to the species radicals. The annealing includes exposing the substrate to molecules, an anneal temperature that is 300 degrees Celsius or greater, an anneal pressure that is within a range of 500 Torr to 550 Torr, and an anneal time that is less than 4.0 minutes.
    Type: Grant
    Filed: January 5, 2022
    Date of Patent: February 13, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Pradeep Sampath Kumar, Norman L. Tam, Dongming Iu, Shashank Sharma, Eric R. Rieske, Michael P. Kamp
  • Patent number: 11901262
    Abstract: Embodiments include a cooling solution having a first array of fins, where the first array of fins extend vertically from the substrate, and where adjacent individual fins of the first array are separated from each other by a microchannel. A second array of fins extend vertically from the substrate, where a channel region is between the first array of fins and the second array of fins.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Nicholas Neal, Zhimin Wan, Shankar Devasenathipathy, Je-Young Chang
  • Patent number: 11901418
    Abstract: Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a diamond layer are sequentially deposited on the III-Nitride layer. Next, a support wafer that includes a GaN layer (or a silicon layer covered by a protection layer) is deposited on the diamond layer. Then, the silicon carrier wafer and the protection layer are removed.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: February 13, 2024
    Assignee: RFHIC Corporation
    Inventor: Won Sang Lee
  • Patent number: 11901417
    Abstract: Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a diamond layer are sequentially deposited on the III-Nitride layer. Next, a substrate wafer that includes a glass substrate (or a silicon substrate covered by a protection layer) is glass bonded to the diamond layer. Then, the silicon carrier wafer and the protection layer are removed.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: February 13, 2024
    Assignee: RFHIC Corporation
    Inventor: Won Sang Lee
  • Patent number: 11888012
    Abstract: Provided is a solid-state image capturing element including a semiconductor substrate and first and second photoelectric conversion parts configured to convert light into electric charge. The first and the second photoelectric conversion parts each have a laminated structure including an upper electrode, a lower electrode, a photoelectric conversion film sandwiched between the upper electrode and the lower electrode, and an accumulation electrode facing the upper electrode through the photoelectric conversion film and an insulating film.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 30, 2024
    Assignees: SONY CORPORATION, SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Kenichi Murata, Masahiro Joei, Fumihiko Koga, Iwao Yagi, Shintarou Hirata, Hideaki Togashi, Yosuke Saito, Shingo Takahashi
  • Patent number: 11876023
    Abstract: Embodiments of the invention provide a method that includes forming an IC layer having an inactive region and an active region. The active region includes a device-under-fabrication (DUF). The inactive region includes a geometric feature having a geometric shape. A film is deposited over the active DUF and the geometric feature such that a first portion of the film will be part of the active DUF, and such that a second portion of the film is over the geometric feature. A geometric shape of the film over the geometric feature matches the geometric shape of the geometric feature. Determining a thickness of the film is based at least in part a difference between a footprint of the geometric shape of the film and a footprint of the geometric shape of the geometric feature.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 16, 2024
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Christopher J. Penny, James John Demarest, Jean Wynne, Christopher J. Waskiewicz, Jonathan Fry
  • Patent number: 11876130
    Abstract: This disclosure describes the structure and technology to modify the free electron density between the gate and drain electrodes of III-nitride semiconductor transistors. Electron density reduction regions (EDR regions) are disposed between the gate and the drain of the transistor structure. In certain embodiments, the EDR regions are created using trenches. In other embodiments, the EDR regions are created by implanting the regions with a species that reduces the free electrons in the channel layer. In another embodiment, the EDR regions are created by forming a cap layer over the barrier layer, wherein the cap layer reduces the free electrons in the channel beneath the cap layer. In another embodiment, a cap layer may be formed in the EDR regions, and doped regions may be created outside of the EDR regions, wherein the impurities act as electron donors.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: January 16, 2024
    Assignee: Finwave Semiconductor, Inc.
    Inventors: Bin Lu, Dongfei Pei, Xiabing Lou
  • Patent number: 11877484
    Abstract: The present disclosure discloses a display panel, a method for preparing the display panel, and a display device. The display panel is divided into a display area and a non-display area. The display panel in the non-display area includes: a substrate; a metal wiring layer arranged on the substrate, the metal wiring layer including metal wirings; a planarization layer covering the substrate and the metal wiring layer, the planarization layer being provided with grooves corresponding to the metal wirings, and the grooves each being located on a side, facing away from the substrate, of a metal wiring corresponding to the each groove and exposing the metal wiring; and a flexible electrode layer filling the grooves, the flexible electrode layer being coupled to the metal wiring layer located at bottoms of the grooves.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: January 16, 2024
    Assignees: Chengdu BOE Optoelectroni cs Technology Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Shuquan Yang, Liqiang Chen
  • Patent number: 11869813
    Abstract: A method of real time leveling control between a superstrate and a substrate is provided. A contact force model indicating a relationship between a total contact force for planarization of a formable material between the superstrate and the substrate and a force component of the total contact force along each of a plurality peripheral axes is identified. A set point force required for performing the planarization is determined. Each force component is calculated based on the contact force model. The planarization is performed by applying each force component along a corresponding axis of the plurality of axes. The contact force model is identified based on a parallel condition between two contacting surfaces of a superstrate chuck for retaining the superstrate and a stack of the superstrate, the substrate, and formable material between the superstrate and the substrate.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: January 9, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventor: Xiaoming Lu
  • Patent number: 11869814
    Abstract: Types, sizes, and locations of crystal defects of an epitaxial layer of a semiconductor wafer containing silicon carbide are detected. Next, a predetermined device element structure is formed and based on location information of the crystal defects of the semiconductor wafer, semiconductor chips free of crystal defects and semiconductor chips containing only extended defects (Frank dislocations, carrot defects) are identified as conforming product candidates among individual semiconductor chips cut from the semiconductor wafer while semiconductor chips containing foreign particle defects and triangular defects are removed as non-conforming chips. Next, electrical characteristics of all the semiconductor chips that are conforming product candidates are checked. Next, based on a conforming product standard obtained in advance, a standard judgment is performed for all the semiconductor chips that are conforming product candidates, whereby semiconductor chips that are conforming products are identified.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: January 9, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hidetatsu Nakamura
  • Patent number: 11869804
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: May 2, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 11869908
    Abstract: A terminal includes a substrate and a photosensitive chip mounted on the substrate, where a side of the photosensitive chip away from the substrate has a photosensitive area and a non-photosensitive area surrounding the photosensitive area, and the photosensitive chip is electrically connected to the substrate by using a metal wire; and the photosensitive chip package structure further includes: a frame, disposed on the side of the photosensitive chip away from the substrate, where an avoidance groove used to avoid the metal wire is disposed on a side of the frame facing the substrate, the avoidance groove extends along a side edge of the frame, and an inner wall of the avoidance groove is an arc-shaped inner wall; and a filling glue, filled in the avoidance groove, and used to wrap the metal wire and bond the frame to the non-photosensitive area of the photosensitive chip and the substrate.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: January 9, 2024
    Assignee: Honor Device Co., Ltd.
    Inventors: Atsushi Yajima, Kun Ran, Zhendong Luo, Lifeng Fu, Weichih Lin, Changfu Huang
  • Patent number: 11864428
    Abstract: A display substrate and a display device are disclosed. In the display substrate, a pixel defining layer includes a plurality of opening groups, each of the opening groups includes a first opening and a second opening, the spacer is located between the first opening of a first opening group row and the second opening of a second opening group row, an orthographic projection of the first opening includes a first long edge, and an orthographic projection of the second opening includes a second long edge, an orthographic projection of the spacer includes a third long edge, and an angle between the third long edge and the first long edge ranges from 20 degrees to 70 degrees, the orthographic projection of the first opening includes a first short edge, and the length of the third long edge is greater than that of the first short edge.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: January 2, 2024
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Hao Zhang, Tingliang Liu, Yu Wang, Huijun Li, Huijuan Yang, Xiaofeng Jiang, Xin Zhang, Jie Dai, Lu Bai, Pengfei Yu, Tinghua Shang
  • Patent number: 11855199
    Abstract: Disclosed is a semiconductor device and a method for fabricating such semiconductor device, specifically a High Electron Mobility Transistor (HEMT) with a back barrier layer for blocking electron leakage and improve threshold voltage. In one embodiment, a semiconductor device, includes: a Gallium Nitride (GaN) layer; a front barrier layer over the GaN layer; a source electrode, a drain electrode and a gate electrode formed over the front barrier layer; a 2-Dimensional Electron Gas (2-DEG) in the GaN layer at a first interface between the GaN layer and the front barrier layer; and a back barrier layer in the GaN layer, wherein the back barrier layer comprises Aluminum Nitride (AlN).
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ling Yeh, Pravanshu Mohanta, Ching-Yu Chen, Jiang-He Xie, Yu-Shine Lin
  • Patent number: 11855135
    Abstract: An object of the disclosure is to provide a semiconductor device having enhanced adhesion of the electrode while improving the reverse direction breakdown voltage, which is especially useful for power devices. A semiconductor device including a semiconductor layer and an electrode layer provided on the semiconductor layer and including at least a first electrode layer and a second electrode layer provided on the first electrode layer, wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer, wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from that of the semiconductor layer, and wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in plan view.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: December 26, 2023
    Assignee: FLOSFIA INC.
    Inventors: Mitsuru Okigawa, Hideaki Yanagida, Takashi Shinohe
  • Patent number: 11848249
    Abstract: There is provided a manufacturing method for a thermal conductive layer, with which a thermal conductive layer having a thermal diffusivity of 3.0×10?7 m2s?1 or more is manufactured on a support by using a composition for forming a thermal conductive layer, the composition containing a resin, a filler, and a solvent and having a concentration of solid contents of less than 90% by mass, the manufacturing method including a discharge step of discharging the composition toward the support; and a solvent amount reduction step of reducing a solvent amount in the composition such that a first solvent amount reduction time taken after the composition is discharged until the concentration of solid contents in the composition reaches 90% by mass on the support is 10 seconds or more for each position on the support.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: December 19, 2023
    Assignee: FUJIFILM Corporation
    Inventors: Kosuke Yamashita, Naotsugu Muro, Toshiyuki Saie, Naoki Sato, Kazuto Shimada
  • Patent number: 11848211
    Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm?3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: December 19, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
  • Patent number: 11842940
    Abstract: A semiconductor structure is provided. The semiconductor structure comprises a heat generating device arranged over a substrate. An interlayer dielectric (ILD) material may be arranged over the heat generating device and the substrate. A metallization layer may be arranged over the interlayer dielectric material. A thermal shunt structure may be arranged proximal the heat generating device, whereby an upper portion of the thermal shunt structure may be arranged in the interlayer dielectric material and may be lower than the metallization layer, and a lower portion of the thermal shunt structure may be arranged in the substrate.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: December 12, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Ramsey Hazbun, Siva P. Adusumilli, Mark David Levy, Alvin Joseph
  • Patent number: 11837656
    Abstract: To provide a nitride semiconductor device excellent in switching characteristics. A nitride semiconductor device includes: a gallium nitride layer having a first principal surface and a second principal surface located on an opposite side to the first principal surface and having a trench formed from the first principal surface to the second principal surface side; and a field effect transistor formed in the gallium nitride layer, wherein the trench has a first side surface and a second side surface inside the trench, the first side surface is a nitrogen face in the surface layer of which nitrogen atoms are located, the second side surface is a gallium face in the surface layer of which gallium atoms are located, and the field effect transistor has: a gate insulating film formed on the first side surface; and a gate electrode formed in the trench and covering the gate insulating film.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: December 5, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Katsunori Ueno, Yuki Ohuchi
  • Patent number: 11823963
    Abstract: A method of real time leveling control between a superstrate and a substrate is provided. A contact force model indicating a relationship between a total contact force for planarization of a formable material between the superstrate and the substrate and a force component of the total contact force along each of a plurality peripheral axes is identified. A set point force required for performing the planarization is determined. Each force component is calculated based on the contact force model. The planarization is performed by applying each force component along a corresponding axis of the plurality of axes. The contact force model is identified based on a parallel condition between two contacting surfaces of a superstrate chuck for retaining the superstrate and a stack of the superstrate, the substrate, and formable material between the superstrate and the substrate.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: November 21, 2023
    Assignee: Canon Kabushiki Kaisha
    Inventor: Xiaoming Lu