Patents Examined by Jack S Chen
  • Patent number: 11401609
    Abstract: A film forming method includes forming a cancel layer on a substrate, which is disposed within a processing container and on which a base film is formed, in a pressure-reduced atmosphere, the cancel layer cancelling orientation of the base film, forming an initial metal film by supplying a metal material gas and a boron-containing gas to the substrate on which the cancel layer is formed, and forming a main metal film on the substrate on which the initial metal film is formed.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: August 2, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koji Maekawa, Katsumasa Yamaguchi, Takashi Sameshima
  • Patent number: 11393714
    Abstract: In a method for producing a buried cavity in a semiconductor substrate, trenches are produced in a surface of a semiconductor substrate down to a depth that is greater than cross-sectional dimensions of the respective trench in a cross section perpendicular to the depth, wherein a protective layer is formed on sidewalls of the trenches. Isotropic etching through bottom regions of the trenches is carried out. After carrying out the isotropic etching, the enlarged trenches are closed by applying a semiconductor epitaxial layer to the surface of the semiconductor substrate.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: July 19, 2022
    Assignee: Infineon Technologies AG
    Inventors: Andre Roeth, Boris Binder, Thoralf Kautzsch, Uwe Rudolph, Maik Stegemann, Mirko Vogt
  • Patent number: 11387146
    Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a first semiconductor fin and a second semiconductor fin formed over a substrate, wherein lower portions of the first semiconductor fin and the second semiconductor fin are separated by an isolation structure; a first gate stack formed over the first semiconductor fin and a second gate stack formed over the second semiconductor fin; and a separation feature separating the first gate stack and the second gate stack, wherein the separation feature includes a first dielectric layer and a second dielectric layer with an air gap defined therebetween, and a bottom portion of the separation feature being inserted into the isolation structure.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: July 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Lun Min, Xusheng Wu, Chang-Miao Liu
  • Patent number: 11387100
    Abstract: A method for manufacturing a mixed substrate having, on a main face of a support substrate, a first region and a second region, includes a) providing a starting substrate which comprises an intermediate layer, consisting of the second material, and the support substrate; b) forming a mask which comprises an aperture delimiting the first region; c) forming a cavity; and d) forming the first region by epitaxially growing the first material in a single crystal form in the cavity The method includes step c1), performed before step d), of forming a protective layer, made of an amorphous material, overlaying the flank of the cavity and leaving the bottom of said cavity exposed to the external environment.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: July 12, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Heimanu Niebojewski
  • Patent number: 11362211
    Abstract: A semiconductor device includes a first active region that extends on a substrate in a first direction, a second active region that extends in parallel with the first active region, an element isolation region between the first and second active regions, a gate structure that extends in a second direction different from the first direction, and intersects the first and second active regions, a lower contact spaced apart from the gate structure in the first direction, the lower contact being on the first active region, the element isolation region, and the second active region, and an upper contact on the lower contact between the first active region and the second active region. A width of the lower contact in the first direction that is on the first active region m narrower than a width of the lower contact in the first direction that is on the element isolation region.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: June 14, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang Young Kim, Deok Han Bae, Byung Chan Ryu, Da Un Jeon
  • Patent number: 11355609
    Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.
    Type: Grant
    Filed: September 10, 2020
    Date of Patent: June 7, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura, Katsuhisa Nagao
  • Patent number: 11355354
    Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor and an oxygen-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The methods may include providing a carbon-containing precursor to the processing region of the semiconductor processing chamber. The carbon-containing precursor may be characterized by a carbon-carbon double bond or a carbon-carbon triple bond. The methods may include thermally reacting the silicon-containing precursor, the oxygen-containing precursor, and the carbon-containing precursor at a temperature below about 650° C. The methods may include forming a silicon-and-oxygen-and-carbon-containing layer on the substrate.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: June 7, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Zeqing Shen, Bo Qi, Abhijit Basu Mallick, Nitin K. Ingle
  • Patent number: 11348826
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: January 23, 2020
    Date of Patent: May 31, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 11340163
    Abstract: A method of detecting a Facet region includes: a fluorescence luminance detecting step of detecting fluorescence luminance unique to SiC by irradiating a SiC ingot with exciting light having a predetermined wavelength from a top surface of the SiC ingot; and a coordinate setting step of setting a region in which the fluorescence luminance is equal to or higher than a predetermined value in the fluorescence luminance detecting step as a non-Facet region, setting a region in which the fluorescence luminance is lower than the predetermined value in the fluorescence luminance detecting step as a Facet region, and setting coordinates of a boundary between the Facet region and the non-Facet region.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 24, 2022
    Assignee: DISCO CORPORATION
    Inventors: Yusaku Ito, Naoki Murazawa, Kazuya Hirata
  • Patent number: 11335808
    Abstract: A semiconductor device including a substrate, a gate structure, a source/drain region, an epitaxial layer, and a spacer wall is provided. The substrate has an upper surface. The gate structure is arranged on the upper surface. The source/drain region is arranged on two sides of the gate structure, is partially embedded in the substrate, and has a tip located in the substrate. A material of the source/drain region includes silicon germanium. The epitaxial layer is arranged between the gate structure and the source/drain region. The spacer wall is arranged on the epitaxial layer on the two sides of the gate structure. A manufacturing method of a semiconductor device is also provided.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: May 17, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Yi-Chung Liang
  • Patent number: 11328939
    Abstract: A method and a device for prefixing substrates, whereby at least one substrate surface of the substrates is amorphized in at least one surface area, characterized in that the substrates are aligned and then make contact and are prefixed on the amorphized surface areas.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: May 10, 2022
    Assignee: EV GROUP E. THALLNER GMBH
    Inventor: Friedrich Paul Lindner
  • Patent number: 11322388
    Abstract: An example method includes patterning a working surface of a semiconductor wafer. The example method includes performing a first deposition of a dielectric material in high aspect ratio trenches. The example method further includes performing a high pressure, high temperature vapor etch to recess the dielectric material in the trenches and performing a second deposition of the dielectric material to continue filling the trenches.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Vivek Yadav, Shen Hu, Kangle Li, Sanjeev Sapra
  • Patent number: 11322606
    Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: May 3, 2022
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Weifeng Sun, Siyang Liu, Sheng Li, Chi Zhang, Xinyi Tao, Ningbo Li, Longxing Shi
  • Patent number: 11316044
    Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: April 26, 2022
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, Adam Brand, John Xia, Chi-Nung Ni, Marco A. Zuniga
  • Patent number: 11309256
    Abstract: A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 19, 2022
    Assignee: SK hynix Inc.
    Inventors: Kun Young Lee, Tae Kyung Kim
  • Patent number: 11302800
    Abstract: A method of making a semiconductor device includes depositing an amorphous layer on a substrate, masking a portion of the amorphous layer, removing a portion of the amorphous layer to form a first channel into the amorphous layer, depositing a semiconductor layer onto the substrate layer, and removing at least a portion of a defect region of the semiconductor layer to form a second channel.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: April 12, 2022
    Assignee: The Texas A&M University System
    Inventors: Michael Everett Babb, Harlan Rusty Harris
  • Patent number: 11302596
    Abstract: A Semiconductor device includes a substrate and a thermal conductive film. The substrate has a top surface and a back surface which oppose with each other. A first opening is formed on the back surface of substrate. The thermal conductive film includes a first thermal conductive portion formed in the first opening. The first thermal conductive portion is embedded in the first opening such that a void is formed in the first opening.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: April 12, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Usami, Hironobu Miyamoto, Masami Sawada
  • Patent number: 11299804
    Abstract: Described herein is a technique capable of suppressing deposits. According to one aspect of the technique, there is provided a method including: (a) supplying a source gas into a process chamber through a source gas nozzle while heating the process chamber; and (b) supplying a reactive gas into the process chamber, wherein (a) and (b) are alternately performed one by one to form a film on the plurality of the substrates while satisfying conditions including: (i) a supply time of the source gas in (a) in each cycle is 20 seconds or less; (ii) a pressure of the source gas in the source gas nozzle in (a) is 50 Pa or less; (iii) an inner temperature of the process chamber in (a) is 500° C. or less; and (iv) number of cycles performed continuously to form the film on the plurality of the substrates is 100 cycles or less.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: April 12, 2022
    Assignee: Kokusai Electric Corporation
    Inventors: Yuji Takebayashi, Kosuke Takagi, Atsushi Hirano, Ryuichi Nakagawa, Noriyuki Isobe
  • Patent number: 11288586
    Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Hubert C. George, Jeanette M. Roberts, Nicole K. Thomas, James S. Clarke
  • Patent number: 11282681
    Abstract: A method of manufacturing a semiconductor device includes placing a substrate in a housing, supplying first gas containing molybdenum to the housing to form a film that contains molybdenum, on the substrate, removing the substrate with the formed film from the hosing, and then supplying second gas containing chlorine to the housing to remove molybdenum deposited on a surface of the housing.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 22, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Katsuaki Natori, Hiroshi Toyoda, Masayuki Kitamura, Takayuki Beppu