Abstract: The invention provides a method for forming a semiconductor structure. The method includes providing a substrate, forming a gate structure on the substrate, respectively forming an epitaxial layer on both sides of the gate structure, and performing a pre-amorphization doping step on the substrate. After the pre-amorphization doping step, a defect is generated in the epitaxial layer, an outer spacer is formed beside the gate structure, and a chemical cleaning step is performed to remove a part of the epitaxial layer, and the defect in the epitaxial layer is removed.

Abstract: A semiconductor device of embodiments includes a silicon carbide layer having a first face and a second face, a gate electrode, a gate insulating layer on the first face. The silicon carbide layer includes a first silicon carbide region of a first conductive type; a second silicon carbide region of a second conductive type disposed between the first silicon carbide region and the first face; a third silicon carbide region of a second conductive type between the first silicon carbide region and the first face; a fourth silicon carbide region; a fifth silicon carbide region; a sixth silicon carbide region of a second conductive type between the first silicon carbide region and the first face and between the second silicon carbide region and the third silicon carbide region; and a crystal defect. The crystal defect is in the sixth silicon carbide region.

Abstract: A substrate processing method of processing a substrate using a gas supplied to a chamber includes: (a) setting a threshold value of a pressure of the gas, which is a control target in a flow rate controller configured to measure the pressure of the gas supplied to the chamber and control a flow rate of the gas; (b) supplying the gas into the chamber; (c) measuring the pressure of the gas by the flow rate controller; (d) stopping the supply of the gas into of the chamber; (e) calculating a time when the pressure of the gas measured in (c) becomes equal to or higher than the threshold value; and (f) calculating a total flow rate of the gas supplied into the chamber based on the pressure of the gas measured in (c) and the time calculated in (e).

Abstract: The present disclosure relates to a display panel (10) and a method of manufacturing the same. The display panel (10) includes a substrate (101), a number of light transmissive units (320), and an package layer (600). The substrate (101) has a light transmissive region (700) and a pixel display region (800). The light transmissive region (700) and the pixel display region (800) are complementarily disposed with respect to the substrate (101). The plurality of light transmissive units (320) are disposed in the light transmissive region (700) and overlay a surface of the substrate (101) within the light transmissive region (700). The package layer (600) overlays a surface of a number of light transmissive units (320). In the present disclosure, the substrate (101) has a different structure in the light transmissive region (700) and the pixel display region (800).

Abstract: An enhancement mode Group III nitride-based transistor device includes a body having a first surface and a Group III nitride barrier layer arranged on a Group III nitride channel layer and forming a heterojunction therebetween. A first cell field includes transistor cells and an edge region. Each transistor cell includes source, gate and drain fingers extending substantially parallel to one another on the first surface in a longitudinal direction. The gate finger, arranged laterally between the source and drain fingers, includes a p-doped Group III nitride finger arranged between a metallic gate finger and the first surface. The edge region surrounds the transistor cells and includes an edge termination structure having an isolation ring and a p-doped Group III nitride runner. The isolation ring locally interrupts the heterojunction. The runner, extending transversely to the longitudinal direction, is located laterally between the isolation ring and an end of the drain finger.

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, depositing a second dielectric layer over the first dielectric layer, recessing the first dielectric layer to define a dummy fin between the first semiconductor fin and the second semiconductor fin, forming a cap layer over top surfaces and sidewalls of the first semiconductor fin and the second semiconductor fin, wherein the forming the cap layer comprises depositing the cap layer in a furnace at process temperatures higher than a first temperature, and lowering the temperature of the furnace, wherein during the lowering the temperature of the furnace, the pressure in the furnace is raised to and maintained at 10 torr or higher until the temperature of the furnace drops below the first temperature.

Abstract: A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

Abstract: A substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has a plurality of silicon single crystal substrates that are joined and has a thickness of more than 2000 ?m, and the plurality of silicon single crystal substrates are produced by a CZ method and have a resistivity of 0.1 ?cm or lower. This provides: a substrate for an electronic device having a nitride semiconductor film formed on a silicon substrate, where the substrate for an electronic device can suppress a warp and can also be used for a product with a high breakdown voltage; and a method for producing the same.

Abstract: A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.

Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.

Abstract: According to one embodiment, a semiconductor device includes a first crystal region, a second crystal region, a third crystal region, and a fourth crystal region. The first crystal region includes magnesium and Alx1Ga1-x1N (0?x1<1). The second crystal region includes Alx2Ga1-x2N (0<x2?1). The third crystal region is provided between the first crystal region and the second crystal region. The third crystal region includes oxygen and Alx3Ga1-x3N (0?x3?1 and x3<x2). The fourth crystal region is provided between the third crystal region and the second crystal region. The fourth crystal region includes Alx4Ga1-x4N (0?x4<1 and x4<x2).

Abstract: A method for producing a semiconductor-on-insulator type substrate includes epitaxial deposition of a first semiconductor layer on a smoothing layer supported by a monocrystalline support substrate to form a donor substrate; production of an assembly by contacting the donor substrate with a receiver substrate; transfer, onto the receiver substrate, of the first semiconductor layer, the smoothing layer and a portion of the support substrate; and selective etching of the portion of the support substrate relative to the smoothing layer. The epitaxial deposition of the first semiconductor layer can be preceded by a surface preparation annealing of the support substrate at a temperature greater than 650° C. After the selective etching of the portion of the support substrate, selective etching of the smoothing layer relative to the first semiconductor layer and epitaxial deposition of a second semiconductor layer on the first semiconductor layer may be carried out in an epitaxy frame.

Abstract: Provided is a method of manufacturing a magnetic tunnel junction that simultaneously realizes removal of oxides on side walls of a magnetic layer and formation of a protective film and prevents deterioration of magnetic characteristics. The method includes: a first step 802 of etching a stacked film including a first magnetic layer, a MgO barrier layer, and a second magnetic layer stacked in order by plasma etching using an oxidizing gas to form the magnetic tunnel junction; and a second step 803 of simultaneously introducing an organic acid gas which is an n-valent acid and a precursor gas having a corresponding metal element valence of m, to form a first protective film on side walls of the magnetic tunnel junction. In the second step, the precursor gas is introduced at a molar ratio of n/m or more with respect to 1 mole of the organic acid gas introduced.

Abstract: A semiconductor structure has a frontside and a backside. The semiconductor structure includes an isolation structure at the backside; one or more transistors at the frontside, wherein the one or more transistors have source/drain electrodes; two metal plugs through the isolation structure and contacting two of the source/drain electrodes from the backside, wherein the two metal plugs and the isolation structure form sidewalls of a trench; and a dielectric liner on the sidewalls of the trench, wherein the dielectric liner partially or fully surrounds an air gap within the trench.

Abstract: A method of manufacturing a semiconductor memory device includes processing a first substrate including a first align mark and a first structure, processing a second substrate including a second align mark and a second structure, orientating the first substrate and the second substrate such that the first structure and the second structure face each other, and controlling alignment between the first structure and the second structure by using the first align mark and the second align mark to couple the first structure with the second structure.

Abstract: Disclosed is a method for manufacturing a semiconductor super-junction device. The method includes: a gate is firstly formed in a gate region of a first trench, then an n-type epitaxial layer is etched with a hard mask layer and an insulating side wall covering a side wall of the gate as masks, and a second trench is formed in the n-type epitaxial layer, and then a p-type column is formed in the first trench and the second trench.

Abstract: A method of fabricating a light emitting device includes (i) determining whether each measurement location is defective or not based on a measurement result of the emission wavelength of each location, (ii) forming a test stacked structure by combining one of the first wafers, one of the second wafers, and one of the third wafers in a set of wafers, and (iii) calculating a combination yield of the test stacked structure based on a count of defective measurement locations that overlap in the test stacked structure.

Abstract: Disclosed is a method for analyzing a shape of a wafer. The method includes measuring external shapes of a plurality of wafers, detecting a first point having a maximum curvature in an edge region of each wafer from measured values acquired in the measuring the external shapes of the wafers, detecting a second point spaced apart from the first point in a direction towards an apex of a corresponding one of the wafers, measuring a first angle formed between a first line configured to connect the first point and the second point and a front side of the corresponding one of the wafers, forming a thin film layer on a surface of each wafer, measuring a thickness profile of the thin film layer, and confirming a wafer in which a maximum value of the thickness profile of the thin film layer is the smallest among the wafers.

Abstract: Making of a transistor structure comprising in this order: forming semiconductor blocks made of SixGe1-x over the surface semiconductor layer and on either side of insulating spacers, the semiconductor blocks having lateral facets, growth of a silicon-based layer over the semiconductor blocks, so as to fill cavities located between said facets and said insulating spacers, thermal oxidation to perform a germanium enrichment of semiconductor portions of the surface semiconductor layer disposed on either side of the spacers.

Abstract: A semiconductor device and method includes: forming a gate stack over a substrate; growing a source/drain region adjacent the gate stack, the source/drain region being n-type doped Si; growing a semiconductor cap layer over the source/drain region, the semiconductor cap layer having Ge impurities, the source/drain region free of the Ge impurities; depositing a metal layer over the semiconductor cap layer; annealing the metal layer and the semiconductor cap layer to form a silicide layer over the source/drain region, the silicide layer having the Ge impurities; and forming a metal contact electrically coupled to the silicide layer.