Abstract: The invention relates to an error correction coding method, using at least two distinct sections of a predetermined elementary code, associating an arrival vector (s2, s3) with a starting state vector (s0, s1), according to a vector of branch labels (b0, b1, b2, b3), defining a code word, two sections of said elementary code being distinct when the order and/or the role of the elements of said branch label vector are changed.

Abstract: The present invention concerns a method and apparatus of decoding a one-point algebraic geometric code defined on an algebraic curve represented by an equation in X and Z of degree 2?? in Z, where ? is a strictly positive integer and ? an integer greater than 1, obtained by taking the fiber product of ? component algebraic equations, each of said component equations governing the unknown X and an unknown Yi, where i=0, . . . , ??1, and being of degree 2? in Yi. This method comprises the decoding of 2(??1)? “clustered” codes, all defined on the same algebraic curve represented by one of said component equations.

Abstract: An apparatus for reproducing data includes a branch metric computation unit and a plurality of parallel computation units. Each parallel computation unit includes path metric computation units that compute path metric values based on branch metric values. Path metric memories store the path metric values to be used in a next following path metric computation, and reliability computation units compute path reliability. Modified-path generating units generate an inverted path that is inverse to a path indicated by an output of the reliability computation units as having low reliability. If any one of the modified-path generating units generates the inverted path, a corresponding one of the path metric computation units stores a path metric value corresponding to the inverted path in a corresponding one of the path metric memories as a path metric value to be used in a next following path metric computation.

Abstract: A triggering circuit asserts a trigger signal in response to edges of a digital signal conveying a repetitive pattern of edges. The triggering circuit generates first data having a value identifying a position within the pattern of a last occurring edge of the digital signal and generates second data having a value identifying a position of a particular edge within the pattern that is to initiate a next assertion of the trigger signal. The triggering circuit asserts the trigger signal when the first and second data values match and de-asserts the trigger signal when the first and second data do not match. In a repetitive mode of operation, the triggering circuit keeps the second data value constant so that it always asserts the trigger signal in response to the same edge of the pattern.

Abstract: A method is presented comprising identifying a weak component in a wireless communication link, instructing a transmitter of the weak component to invoke repetition coding, and selectively combining signals received via multiple antennae on multiple channels to recover information contained in the transmitted signal.

Abstract: On chip diagnosis method and on chip diagnosis block with mixed redundancy (IO redundancy and word-register redundancy) is provided. During a BIST (Built-In Self Test), information needed to apply redundancy resources is stored inside two arrays (fill_array, shift_array) on chip. A final diagnosis may apply redundancy resources based on this stored information. The first array (fill_array) is used to keep a minimum error mapping and the second array (shift_array) is used to control the fill of the first array.

Abstract: A testing procedure for distributed logic circuits that incorporates an efficient utilization of flip-flops to toggle detect for sensing output is discussed. The distributed logic circuit is a phase interpolator or a phase interpolator preceded by a DLL. The testing procedure utilizes enabling one of a plurality of independent programmable current sources and a flip-flop to toggle in response to the enabled current source to indicate a physical connection of the enabled distributed logic circuit current source.

Abstract: In order to test digital modules with functional elements, these are divided into test units (3) which respectively have inputs and outputs. Alternating test patterns are applied to the inputs of the test unit (3), and the test responses resulting from this are evaluated at the outputs of the test unit (3). The effect is then encountered that changes at each of the inputs of a test unit (3) do not all affect a particular output of this test unit (3). For every output of the test unit (3), it is possible to define a cone (5) whose apex is formed by the particular output of the test unit (3) and whose base comprises the inputs of the test unit (3) where, and only where, changes affect the particular output. According to the invention, the test pattern to be applied to the inputs of the test unit (3) is constructed of sub-patterns, whose length is in particular ? the number of inputs of the test unit (3) that are contained in the base of a cone (5).

Abstract: A test module is provided for testing system modules. All the test circuitry and test connectors reside on the test module. The test module is coupled to the system modules during testing, and is removed from the system after testing. Test connectors and test circuitry on the test module support such test functions as voltage margining, CPU emulation, and JTAG boundary scanning. A JTAG selection function can also be provided for selecting one or more JTAG loops for testing individually or as a single loop. The test module further includes level shifters for converting between 3.3V and 1.2V.

Abstract: Embodiments of the invention include a method and apparatus for encoding data and a system for transmitting and/or storing data, in which the data is encoded and precoded in a manner that does not violate previously established data constraints, such as modulation encoding constraints. The method includes the steps of modulation encoding the data using a modulation code defined by at least one modulation constraint, parity encoding the modulation encoded information, and precoding the encoded information. The precoding step either partially precodes information bits and precodes parity bits, precodes information bits but not parity bits, or precodes both information bits and parity bits in such a manner that does not violate modulation constraints. Also, the parity encoding step can be performed in such a manner that does not violate modulation code constraints.

Abstract: A method and system for scanning data from a specific latch in a matrix array of latches. The matrix array is made up of vertical selector lines and horizontal data lines. Each latch is coupled at an intersection of a selector line and a data line by a transistor. By turning on the transistor, the contents of the latch can be selectively read or written to.

Abstract: The invention concerns a circuit protected against transitory perturbations, comprising a combinatorial logic circuit (10), having at least an output (A); a circuit (20) generating an error control code for said output, and a storage element (24) provided at said output, controlled by the circuit generating a control code to be transparent when the control code is correct, and to maintain its status when the control code is incorrect.

Abstract: A semiconductor circuit apparatus, on which a scan test can be conducted, has a plurality of circuit sections. The semiconductor circuit apparatus includes a scan chain having a plurality of flip-flops for transmitting test data. The semiconductor circuit apparatus also has a first macro cell placed in a path between flip-flops included in the scan chain, a first bypass path bypassing the first macro cell, a first selection circuit selecting the first macro cell or the first bypass path, a second macro cell placed in a path between flip-flops included in the scan chain, a second bypass path bypassing the second macro cell, and a second selection circuit selecting the second macro cell or the second bypass path. The first selection circuit and the second selection circuit operate individually.

Abstract: Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

Abstract: To facilitate a processor during a reset operation, a linked list of pointers to a list of defective cache lines is created. The good data bits in defective cache lines are used for creating a linked list or other data structure for storing relevant information regarding defective cache lines.

Abstract: The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial. The two dimensional parity is used to protect, locate and correct errors automatically. The second parity is provided for only a subset of the address range of the memory. The memory controller does not compare the second parities unless there is a soft error in the first parity. The second parities are calculated upon command and not upon each memory write as the first parity.

Abstract: The present invention relates to the architecture and operation of computer hardware memory logic, and in particular to a method and respective system for verifying hardware memory logic, wherein an Error Correction Code (ECC) is used for correcting single-bit or multi-bit errors when the ECC-bits cannot be accessed directly for a read or write process. The system and process employs the selection of data patterns that produce check bits that are all ones to ferret out errors in the ECC circuitry.

Abstract: An apparatus and method for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy data from each subsequent test in the same bank of eFuses, a latch on a scan chain is used that holds the programming information for each eFuse. This latch allows for programming only a portion of eFuses during each stage of testing. Moreover, the data programmed in the eFuses can be sensed and read as part of a scan chain. Thus, it can be easily determined what portions of the bank of eFuses have already been programmed by a previous stage of testing and where to start programming the next set of data into the bank of eFuses. As a result, the single bank of eFuses stores multiple sets of data from a plurality of test stages.

Abstract: A semiconductor testing apparatus, includes a test signal generating unit that generates a test signal corresponding to a test pattern to output the generated test signal to a device under test (DUT); a comparison signal generating unit that generates a comparison signal by combining a reference signal and the test signal; and a comparing unit that compares a response signal, which is output from the DUT in response to the input of the test signal, and the reference signal by offsetting the test signal contained in a composite signal of the test signal and the response signal and the test signal contained in the comparison signal. The DUT is determined to be defective or not based on a result of comparison by the comparing unit.

Abstract: A parallel decoder, which is simpler and more flexible than conventional devices, is provided in decoding device for a LDPC code. The present invention includes a plurality of memory units for storing a received value and a message generated during a Message-Passing decoding, a plurality of variable node function units, a plurality of check node function units, a plurality of address generation units for generating an address of each of memory units, and a plurality of shuffle network units for determining a connection between variable node function units and check node function units. An address generation unit generates an address on the basis of a plurality of permutations. Each shuffle network unit is connected to some of the variable node function units. This connection is determined on the basis of a plurality of permutations. A change of the permutations in the address generation units and a change of the permutations in the shuffle network units are performed in the same cycle in a decoding process.