Abstract: A system for soft-decoding of Reed-Muller coded information has one or more rows of decoding blocks, each decoding block having a soft-output device and a Reed-Muller message passing device. A first soft-output device of a first decoding block processes a coded signal and a zero value probability vector. Each subsequent soft-output device processes the coded information and a non-zero value probability vector. The system for soft-decoding Reed-Muller coded information decodes a code-bit reliability vector from a soft-output device to generate an updated codeword reliability vector, which is used by a next decoding block in a sequence of decoding blocks to reprocess the coded information using the updated reliability vector. The reliability vector is updated through processing in each decoding block to optimize the reliability vector for extraction of the transmitted information from the received information.

Abstract: A method and system for making error corrections on digital information coded as symbol sequences, for example digital information stored in electronic memory systems or transmitted from and to these systems is described, provides the transmission of sequences incorporating a portion of error corrector code allowing the sequence which is more probably the original transmitted through the calculation of an error syndrome using a parity matrix to be restored when received. Advantageously according to embodiments of the invention, the error code incorporated in the original sequence belongs to a non Boolean group.

Abstract: A disk array system is provided, which can improve data reliability by verifying addressing correctness of data access by applying a redundant code to user data even if using an HDD compatible with serial ATA, etc. whose sector length cannot be extended. When writing the object data to an HDD, a controller stores partly-extracted data of the object data in a control area and performs an XOR operation between the partly-extracted data and a check code generated by calculations. Then, the operation-resultant data (CC-embedded data) are returned to the object data and written in the HDD. Also, when reading the object data from the HDD, the controller fetches the CC-embedded data, performs an XOR operation between the fetched data and the check code, and compares and collates the operation-resultant data with the partly-extracted data in the control area to check the addressing correctness and restore the user data.

Abstract: A circuit, a method, and a method of designing the circuit, the circuit including: multiple W-bit packet data slice latches; a data partition comprising multiple data XOR subtree levels and having data latches between the data XOR subtree levels; a remainder partition comprising multiple remainder XOR subtree levels and having remainder latches between the remainder XOR subtree levels; a combinatorial XOR tree, outputs of the remainder partition and outputs of the data partition connected to inputs of the combinatorial XOR tree; and a remainder latch, combinatorial XOR tree connected to the remainder latch and the outputs of the remainder latch connected to the remainder partition.

Abstract: A transmitter uses an adaptive forward error control scheme that includes redundant packets to reduce packet error rate at a receiver. The receiver analyzes the received packet error rate before correction to determine an optimal level of redundancy required to respect a maximum tolerated packet error rate after correction, and communicates this determined optimal level to the transmitter for controlling the amount of redundancy in subsequent transmissions from the transmitter.

Abstract: The present invention relates to a pre-processing apparatus using nonuniform quantization of a channel reliability value and a low density parity check (LDPC) decoding system. The pre-processing apparatus can present degradation in performance and be embodied simply by performing decoding pre-process by estimating a discrete channel reliability value (Lc*) through nonuniform quantization of a channel reliability value based on a relations between a bit error rate (BER) estimated through a simulation performed in advance and a standard deviation (?) of channel noise within a predetermined range of noise estimation error and p, and bit-shifting a receiving signal as much as a discrete channel reliability value. The pre-processing apparatus includes: a channel reliability measuring unit, a nonuniform quantizing unit, a sign bit adding unit, a bit shifting unit.

Abstract: A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.

Abstract: Embodiments of the present invention relate to a method. The method includes synchronizing a first device and a second device. If the first device and the second device both initiate the synchronizing at substantially the same time, then the first device and/or the second device may compensate for synchronization errors. In other words, when two devices begin communication, one or both the devices may perform a procedure which causes the two devices to successfully synchronize. Accordingly, when the two devices are synchronized they will be able to communicate. However, if both devices initiate synchronization at substantially the same time, absent additional measures, the two devices may not be synchronized. Accordingly, in embodiments of the present invention, these synchronization errors are compensated for, if a first and second device both initiates a synchronization procedure at substantially the same time.

Abstract: A threshold value is set in a decision circuit receiving a transmitted stream of binary symbols from a network link. The decision circuit uses the threshold value for detecting whether a 1 or a 0 is received to produce an output stream having a low bit error rate. Bit errors in the output stream of the detector are detected. The number of errors is counted when a transmitted 0 is detected as a 1 in the output stream. The number of errors is also counted when a transmitted 1 is detected as a 0 in the output stream. The counted numbers of errors are compared to each other. The threshold value is modified, if necessary, based on the result of the comparing, to e.g. make the probabilities of the two kinds of errors equal to each other. Extra predetermined bits can be inserted and used in determining bit errors.

Abstract: The present invention provides an apparatus and method for controlling transmission powers of R-CQICH (reverse-channel quality indicator channel) and R-ACKCH (reverse-acknowledgment channel) independently. The present invention includes the steps of receiving a first parameter corresponding to the R-CQICH and a second parameter corresponding to the R-ACKCH from a base station via an overhead message and independently determining transmission powers of the R-CQICH and the R-ACKCH using the first and second parameters.

Abstract: A boundary scan register circuit and a method of characterization testing. The boundary scan register circuit, including: a multiplicity of boundary scan cells connected in series, each boundary scan cell having a latch; means for isolating the boundary scan cells into one or more boundary scan segments, each boundary scan segment containing a different set of the boundary scan cells; and means for characterizing signal propagation through each boundary scan segment.

Abstract: Error tolerance is increased for a storage system having a plurality of arrays by making local redundancy in a selected array globally available throughout the storage system. To achieve the increased error tolerance, a donor array is selected from the plurality of arrays when the difference between a minimum Hamming distance of the donor array and a minimum Hamming distance of a recipient array is greater or equal to 2. A donor storage unit is selected in the donor array and recipient information is then rebuilt from the recipient array on the selected storage unit. The selected storage unit is indicated to the donor array as having been donated before the lost information is rebuilt on the selected storage unit. Preferably, the minimum Hamming distance of the recipient array is d?2 before the donor array is selected from the plurality of arrays.

Abstract: A method of block puncturing for turbo code based incremental redundancy includes a first step (1200) of coding an input data stream into systematic bits and parity bits. A next step (1202) includes loading the systematic bits and parity bits into respective systematic and parity block interleavers in a column-wise manner. A next step (1204) includes selecting a predefined redundancy. A next step (1206) includes outputting bits from the block interleavers in a row-wise manner in accordance with the selected predefined redundancy.

Abstract: A method and apparatus for use in encrypting and decrypting digital communications converting an initial block to final block based on freely selectable control information and secret key information having double the length of prior art keys and maintaining compatibility with the prior art encryption system.

Abstract: The present invention provides for an icon with an additional level of functionality that allows a user to validate that current information (e.g., a web page) originates from the true owner of the icon and is not merely a copy. The method includes a user requesting a web page from a web site using a web browser. The web server receives the request, retrieves the web page and forwards it to an authentication server. The authentication server inserts an authenticity key into the web page, then the page (including the authenticity key) is returned to the user. If the page includes an authenticity key, the authenticity is verified at the user's computer because the user computer includes logic (e.g., software) to verify the authenticity. During the user configuration process, the user defines an authenticity stamp which determines the format of an authenticated page.

Abstract: A symmetric-key cryptographic technique capable of realizing both high-speed cryptographic processing having a high degree of parallelism, and alteration detection. The invention includes dividing plaintext composed of redundancy data and a message to generate plaintext blocks each having a predetermined length, generating a random number sequence based on a secret key, generating a random number block corresponding to one of the plaintext blocks from the random number sequence, outputting a feedback value obtained as a result of operation on the one plaintext block and the random number block, the feedback value being fed back for using in the operation on another plaintext block, and performing an encryption operation using the one plaintext block, random number block, and feedback value.

Abstract: An apparatus for authenticating memory space of an authorized accessory of a device includes an integrated circuit. The integrated circuit is configured to define two secret keys K1 and K2, a random function which returns a random number R and a first parameter being a function of the random number R using the secret key K1 of the integrated circuit and to define a test function operable on data using the secret key K2 of the integrated circuit to return a one or a zero. A control system is configured to call the random function of the integrated circuit, to call a read function defined by the accessory using a function of R with the secret key K1 stored by the accessory as a second parameter, such that the accessory returns a third parameter from the memory space which is a function of R using the secret key K2 stored by the accessory if the first and second parameters are equivalent, to call the test function using a function of R with the secret key K2 of the integrated circuit as a fourth parameter.

Abstract: An apparatus and method for selectively encrypting portions of data sent over a network between a server and a client. The apparatus includes parsing means for separating a first portion of the data from a second portion of the data, encrypting means for encrypting only of the first portion of the data, and combining means for combining the encrypted first portion of the data with the second portion of the data, wherein the second portion of the data is not encrypted. The apparatus further includes decrypting means installed at the client for decrypting the encrypted portion of the data. The apparatus is platform independent in terms of media format and data protocol. The encryption unit encrypts data transparently to the client based on the media format. The apparatus of the invention is implemented as one of an application and a plug-in object.

Abstract: An electronic data management system for accurately determining the authenticity of the electronic data and the specification of the source of unauthenticated electronic data. A drawing output processor transmits original electronic drawing data A1 to an order receiving unit with a tag T attached. The order receiving unit and a manufacturing unit transmit a manufacturer's copied data B2(T) copied from the original data A1(T) to an inspection unit. The inspection unit transmits the inspection result Fa for the product M, the client's copied data A2 re-copied from the original data A1, and the manufacturer's copied data B2 (T) to a determination unit. The determination unit compares the tag T extracted from the manufacturer's copied data B2 with the original value of the client's copied data A2 and the original value of the manufacturer's copied data B2 and determines the authenticity of the client's copied data A2 and the manufacturer's copied data B2.

Abstract: A storage device includes a tamper-resistant module and a flash memory. In correspondence with a command, a CPU inside the tamper-resistant module judges the security of data received from the outside, then recording the data as follows: High-security and small-capacity data is recorded into a memory inside the tamper-resistant module. High-security and large-capacity data is encrypted, then being recorded into the flash memory. Low-security data is recorded as it is into the flash memory. This recording method permits large-capacity data to be stored while ensuring a security (i.e., a security level) corresponding thereto.