Abstract: A semiconductor memory device includes a memory array having a data area and a check code area and a refresh control for controlling a refresh operation in a data holding state. The device also includes an operation system for executing an encoding operation for generating the check code using a bit string in the data area and a decoding operation for performing the error detection/correction of the data using the check code. Additionally, the device includes an encode controller for controlling an encode process in which, in a change to the data holding state, a first and second code are written in the check code area. Furthermore, the device includes a decode controller for controlling a decode process in which, at the end of the data holding state, first and second bit error correction based on each code are alternately performed, and the first and the second bit error correction are performed at least twice respectively.

Abstract: A testing system includes a phase interpolator receiving a clock signal. An output of the phase interpolator is coupled to both a first signal distribution tree that includes a first delay line in each of its branches and a second signal distribution tree that includes a second delay line in each of its branches, thereby producing respective first and second delayed clock signals. A test signal generator generates a plurality of test signals that may simulate memory command or address signal. A multiplexer couples the test signals to first and second inputs of a transmitter in a normal test mode but to only the first input in a special test mode. The transmitter outputs the signal applied to its first input responsive to the first delayed clock signal and it outputs the signal applied to its second input responsive to the second delayed clock signal.

Abstract: Disposed on both sides of a parity cell array are a first regular cell array and a sub parity generation circuit therefor, and a second regular cell array and a sub parity generation circuit therefor. The sub parity generation circuit generates sub parity data according to read data that are simultaneously read from the first and second regular cell arrays. A main parity generation circuit generates according to sub parity data parity data in common to the regular cell arrays, is not disposed in a distributed manner but disposed corresponding to the parity cell array. Thus, the layout design, layout verification, and so forth of a semiconductor memory can be prevented from being complexed. As a result, the parity generation circuit can be optimally laid out, decreasing the development time and defect analysis time for the semiconductor memory can be decreased.

Abstract: A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the offset, timing, and current compensation with a loopback control register. The slave and master agent to support an entry into the loopback test based on detection of a header within a packet. The slave and master agent to support exit out of the loopback test based on whether the loop count is finite.

Abstract: Test functions are expanded by adopting a self test part, and circuit scale is reduced by adding the self test part. A semiconductor integrated circuit includes a memory that includes plural memory banks and is accessed by specifying a bank address, an X address, and a Y address, and a self-test part that tests the memory in response to commands. The self-test part has an address counter covering plural addressing modes that are different in the updating of X addresses, Y addresses, and bank addresses. A variety of addressing modes provided expand BIST-based test functions.

Abstract: Methods and apparatus provide a transceiver, such as a serializer/deserializer device (SerDes), with enhanced built-in self test (BIST). A built-in self test circuit is provided that decouples a clock signal used for receiving data from a clock signal used in transmitting data. This permits data tracking circuitry of a receiver to be efficiently tested with a relatively simple loop back test.

Abstract: There is provided a pattern generator that generates a test pattern for testing an electronic device using test data previously supplied. The pattern generator includes a cache memory, a main memory operable to store a plurality of test data blocks of which each block is the test data of the magnitude capable of being stored on the cache memory, and an instruction memory operable to store instruction information showing sequence in which the plurality of test data blocks should be stored on the cache memory, in which the pattern generator sequentially outputs the test data blocks stored on the cache memory as the test pattern. It is preferable that the instruction memory stores the instruction information showing all sequence of the test data blocks to be stored on the cache memory in order to generate the test pattern before beginning to generate the test pattern.

Abstract: A method and apparatus for editing outbound frames and generating acknowledgements for a TCP connection is described. Acknowledgements are automatically generated and included in outbound frames during data transmissions with minimal processor intervention.

Abstract: An information storage medium includes a drive zone having a plurality of physical clusters or ECC blocks. When new drive data is recorded in the drive zone, the new drive data is recorded in a physical cluster or ECC block next to the physical cluster or ECC block containing the most recently recorded drive data. In the method of recording drive data, the drive data is recorded in a physical cluster or ECC block of the drive zone. When the drive zone is updated with the new drive data, the new drive data is recorded in the physical cluster or ECC block adjacent to physical cluster or ECC block containing the most recently drive data. The drive data recording method is applicable to a new format of information storage medium.

Abstract: Redundant storage of computer data including encoding N data values through M linear expressions into M encoded data values and storing each encoded data value separately on one of M redundant storage devices where M is greater than N and none of the linear expressions is linearly dependent upon any group of N?1 of the M linear expression.

Abstract: The invention concerns a frequency-domain error concealment technique for information that is represented, on a frame-by-frame basis, by coding coefficients. The basic idea is to conceal an erroneous coding coefficient by exploiting coding coefficient correlation in both time and frequency. The technique is applicable to any information, such as audio, video and image data, that is compressed into coding coefficients and transmitted under adverse channel conditions. The error concealment technique proposed by the invention has the clear advantage of exploiting the redundancy of the original information signal in time as well as frequency. For example, this offers the possibility to exploit redundancy between frames (inter-frame) as well as within frames (intra-frame). The use of coding coefficients from the same frame as the erroneous coding coefficient is sometimes referred to as intra-frame coefficient correlation and it is a special case of the more general frequency correlation.

Abstract: A method, apparatus and computer program product are provided for implementing scan-chain-specific control signals as an integral part of a scan chain. A scan input vector including scan data input and a scan control signal is applied to a register latch that forms the scan chain. The register latch includes a logic gate for combining a global clock control (THOLD) signal and the scan control signal. The scan control signal is routed around the register latch and including in a scan output vector including scan data output. Chain-specific control signals are eliminated from a clock control signal distribution tree used with the scan chain of the invention.

Abstract: An optical disk playback apparatus for playing back or reproducing main data and its associated sub-code which are read from an optical recording medium comprises an interleave RAM for storing the main data. The optical disk playback apparatus performs a predefined synchronization protection on synchronization information included in the sub-code to generate a sub-code synchronization signal which is written into an empty area of the interleave RAM, and manages the addresses with a FIFO area in a manner similar to the main data, thereby causing the read sub-code synchronization signal to function in synchronization with the main data.

Abstract: Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.

Abstract: A skew adjustment circuit employs a novel algorithm enabling a reduction in scale of the circuit of a receiver for a Transition Minimized Differential Signaling (T.M.D.S.) link in accordance with the Digital Visual Interface (DVI) standard. The skew adjustment circuit includes a sampling point selection section that performs comparison processing on oversampled data, assumes transition points of serial data, and outputs a sampling point selection signal; and a data recovery section that outputs oversampled data at the sampling point selected by the selection signal, as sample data for the serial data. Comparison processing is performed on the oversampled data in 4-bit segment units of the serial data, transition point detection signals are held, and the transition points of the serial data are assumed based on those transition point detection signals, when transition point detection signals for at least two segments, which are among the held transition point detection signals, indicate the same result.

Abstract: A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words written to the DRAM, and thereby achieves a low syndrome bit overhead. The memory controller may write data words to the DRAM having less than 128 bits by first reading 4 32-bit words from the DRAM, substituting the write data for a corresponding number of bits of read data, and writing the new 128-bit word to the DRAM by writing 4 32-bit words.

Abstract: A method and device perform error detection with partial checksum coverage by using a first transport protocol, wherein interface means are provided for requesting from a second lower-level transport protocol at least one lower-level header field to be subjected to checksum calculation over a predetermined portion of a data packet of the first transport protocol and the requested lower-level header fields. A checksum-based error processing function of the lower-level second transport protocol is disabled during the transmission of the data packet. Thereby, a checksum with partial coverage can be carried inside a higher-level data packet to provide Unequal Error Detection (UED) for error tolerant applications without requiring modifications of lower layer protocols.

Abstract: A method and system for performing diagnostic tests on a real-time system controlled by a state machine. A sequence of states recorded as the state machine operates is used to determine error conditions. The sequence of states is compared to expected sequences of states to determine what, if any, errors have occurred. If the real-time system, such as a transceiver in a communication system, has adaptive components, the status of the adaptive components is used to estimate the condition of any external systems coupled to the real-time system.

Abstract: The invention concerns a method (500) for tracking sequence numbers. The method includes the steps of detecting (512) an error in a first set of data (120), determining (514) a range (144) of possible sequence numbers (122) for a second set of data (120) and using the range of possible sequence numbers, producing (516) a block code (126) for the second set of data in which the block code is used to verify that one of the range of possible sequence numbers is a correct sequence number for the second set of data.

Abstract: A test pattern generating apparatus comprises a circuit data read in section 11 that divides circuit data into a plurality of functional blocks, a correspondence setting up table preparing section 12 that sorts the plurality of functional blocks into test pattern generating object blocks and test pattern copying object blocks that are configurationally identical with the test pattern generating object blocks and sets up correspondence of the test pattern generating object blocks to the test pattern copying object blocks, a test pattern generating section 13 that generates a test pattern of each of the test pattern generating object blocks and a test pattern copying section 14 that copies the test pattern of each of the test pattern copying object blocks and uses it as test pattern of the test pattern copying object block.