Patents Examined by Jae U Yu
  • Patent number: 10976966
    Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. The computing devices may use local caches in a coherent manner when accessing the plurality of storage devices.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: April 13, 2021
    Inventors: Maor Ben Dayan, Omri Palmon, Liran Zvibel, Kanael Arditti, Artemy Voikhansky, Alex Goltman
  • Patent number: 10969981
    Abstract: An information processing device includes a memory, and a processor configured to perform a first process configured to generate control data used in communication and storing the generated control data in a locked state in the memory while performing start processing of the first process, release the locked state of the control data in response to completion of the start processing or suspension of the start processing, and communicate with a communication device in response to a communication request, and perform a second process configured to determine, based on the control data, whether connection with the first process is established, when it is determined that the connection with the first process is not established, select processing for connecting with the first process in accordance with whether the control data in the memory is locked, and transmit the communication request to the first process while connecting with the first process.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: April 6, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Yuki Ikeda
  • Patent number: 10963349
    Abstract: Techniques are disclosed that permit storage and availability operations, such as backup and restore, snapshot and cloning, application disaster recovery, and reporting and analytics, to be performed for stateful containerized applications. In one embodiment, a container cluster service is configured to create application instance objects that capture metadata associated with containerized applications and that (optionally) specify scripts to be run before and/or after taking an application consistent snapshot and/or an order in which to take snapshots. Application instances having the configurations specified in the application instance object may then be deployed.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: March 30, 2021
    Assignee: VMware, Inc.
    Inventors: Prashant Dhamdhere, Prashima Sharma, Mark Sterin, Sandeep Srinivasa Rao Pissay
  • Patent number: 10965665
    Abstract: Systems and methods for network security are provided. Various embodiments of the present technology provide systems and methods for an identity security gateway agent that provides for privileged access. Embodiments include a system and method that uses a single sign-on (SSO) (or similar) mechanism to facilitate a user accessing web-based service providers, but separates the assertion and entire SSO process from the user credential.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: March 30, 2021
    Assignee: SAILPOINT TECHNOLOGIES, INC
    Inventors: Ryan Privette, Kris Keller
  • Patent number: 10956084
    Abstract: According to one embodiment, a method, computer system, and computer program product for adjusting tiering based on operation types in a multi-tier storage system is provided. The present invention may include retrieving an extent to be managed and operations associated with the extent; analyzing the operations of the extent to determine an IO pattern associated with the extent; receiving a list of storage devices within the multi-tier storage system; querying each storage device of the storage devices for suitable pattern types; selecting, based on the querying and the IO pattern associated with the extent, a suitable storage device; and transferring the extent to the suitable storage device.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: March 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander H. Ainscow, Duo Chen, John M. Clifton, Kushal Patel, Sarvesh Patel
  • Patent number: 10956066
    Abstract: Non-volatile memory having a non-volatile memory array adapted to store a configuration routine for a low power dynamic random access memory (LPDRAM), a memory interface for receiving addresses from an external device for access of data stored in the non-volatile memory array, and an internal controller adapted to communicate with a LPDRAM coupled to the non-volatile memory and configure operational settings of the LPDRAM using the configuration routine, as well as systems containing similar non-volatile memory.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 10956061
    Abstract: A computing system includes: a host configured to provide data and address information on the data; and a memory system configured to store the data, wherein the memory system comprises: a plurality of memory devices configured to be grouped into at least one memory device group; and a controller configured to control each of the plurality of memory devices, wherein the controller comprises: a group setter configured to set the memory device groups with respect to a type of the data by a request of the host; and a processor configured to read the data from, or write the data to, the memory device group corresponding to the type of the data.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Jun-Seo Lee
  • Patent number: 10949359
    Abstract: Determining storage of particular data in cache memory of a storage device includes using a first mechanism to determine when to remove the particular data from the cache memory and using a second mechanism, independent from the first mechanism, to inhibit the particular data from being stored in the cache memory independent of whether the first mechanism otherwise causes the particular data to be stored in the cache memory. The first mechanism may remove data from the cache memory that was least recently accessed. The second mechanism may be based, at least in part, on a prediction value of an expected benefit of storing the particular data in the cache memory. The prediction value may be determined based on input data corresponding to measured cache read hits (RH), cache write hits (WH), cache read misses (RM), cache write destage operations (WD), and prefetch reads (PR) for the particular data.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: March 16, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Owen Martin, Kaustubh S. Sahasrabudhe, Mark D. Moreau, Malak Alshawabkeh, Earl Medeiros
  • Patent number: 10929025
    Abstract: In a data storage system, latency optimization can be practiced by logging a plurality of data accesses to a memory in a register with each data access of the plurality of data accesses corresponding with a command generated by a host connected to the memory. The register may be analyzed with a system module to predict a command execution latency value for the plurality of data accesses that can be used to generate a deterministic data access sequence with the system module. A queue of data accesses can then be reorganized from a first sequence to the deterministic data access sequence to reduce command execution latency variability during a deterministic window selected by the host.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: February 23, 2021
    Assignee: Seagate Technology LLC
    Inventor: Michael Shaw
  • Patent number: 10929028
    Abstract: A control device for controlling a memory device to process requests from a plurality of hosts may include a request controller configured to manage a set representing storage space allocated to each of the plurality of the hosts; and a set controller configured to monitor requests from the plurality of hosts and to adjust size of the set, wherein, when the request is a write request from a host among the plurality of hosts, the request controller selects a target physical address among physical addresses included in the set allocated to the host, the target physical address indicating where the request is to be processed.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: February 23, 2021
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Bryan Suk Joon Kim, Sang Lyul Min
  • Patent number: 10929064
    Abstract: An operational method of a memory module is provided. The method includes receiving, from an external of the memory module, a first command and a first address in synchronization with clock signals. Status information is output through a signal line, when first data corresponding the first address is available in a data buffer in response to the first command. A second command in synchronization with the clock signals after the transmitting the status information is received from the external of the memory module, a second command. In response to the second command, the first data being available in the data buffer is output through data lines.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: February 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjin Cho, Hee Hyun Nam, Hyo-Deok Shin, Junghwan Ryu
  • Patent number: 10922003
    Abstract: A host-assisted data deduplication system, including: a storage device including a controller, memory, and a write cache; and a host including a data duplication module coupled to the storage device, wherein the controller of the storage device is configured to write a data sector received from the host into the write cache in the storage device and to send a write completion to the host immediately after writing the data sector to the write cache; wherein the data duplication module is configured to detect whether the data sector is identical to another data sector stored in the memory of the storage device and to asynchronously send a duplicate detection result to the controller of the storage device, and wherein the controller of the storage device is configured to perform a data deduplication process for the data sector stored in the write cache based on the duplicate detection result.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: February 16, 2021
    Assignee: SCALEFLUX, INC.
    Inventors: Tong Zhang, Yang Liu, Fei Sun, Hao Zhong
  • Patent number: 10922235
    Abstract: A system and method are disclosed for handling logical-to-physical mapping and increasing the amount of mapping table information that may be stored in a cache in volatile memory. The system includes a storage device having non-volatile memory, an input/output interface, a cache manager, a cache utilization manager, a cache swap manager, and a storage controller configured to service a storage command using a physical address provided by the cache manager. The method includes receiving a storage command comprising a logical address, the logical address comprising a partition identifier, implementing a cache eviction policy in response to determining that a mapping table cache does not have a cache entry that matches the logical address. The method also includes evicting the cache entry with a ranking, or score, that satisfies a cache eviction threshold and loading a replacement cache entry from an address mapping table stores on non-volatile memory.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 16, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ariel Navon, Shay Benisty, Eran Sharon
  • Patent number: 10901902
    Abstract: Methods and systems for cache management are provided. Aspects include providing a drawer including a plurality of clusters, each of the plurality of clusters including a plurality of processor each having one or more cores, wherein each of the one or more cores shares a first cache memory, providing a second cache memory shared among the plurality of clusters, and receiving a cache line request from one of the one or more cores to the first cache memory, wherein the first cache memory sends a request to a memory controller to retrieve the cache line from a memory, store the cache line in the first cache memory, create a directory state associated with the cache line, and provide the directory state to the second cache memory to create a directory entry for the cache line.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: January 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chad G. Wilson, Robert J Sonnelitter, III, Tim Bronson, Ekaterina M. Ambroladze, Hieu T Huynh, Jason D Kohl, Chakrapani Rayadurgam
  • Patent number: 10895991
    Abstract: Aspects of the disclosure provide a data storage apparatus that includes a non-volatile memory (NVM) and a controller. The NVM includes a first NVM portion and a second NVM portion. The first NVM portion includes a plurality of first cell types. The first NVM portion includes a first sub-portion that is allocated to store file management data. The second NVM portion includes a plurality of second cell types. The controller is coupled to the NVM. The controller is configured to receive a plurality of payload data and a plurality of file management data; store the plurality of file management data at the first sub-portion of the first NVM portion; and store the plurality of payload data at the NVM.
    Type: Grant
    Filed: November 14, 2018
    Date of Patent: January 19, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Vishwas Saxena, Abhijit K. Rao, Saifullah Mohiddin Nalatwad, Sameer Hiware
  • Patent number: 10877882
    Abstract: Systems and methods for adapting garbage collection (GC) operations in a memory device to a pattern of host accessing the device are discussed. The host access pattern can be represented by how frequent the device is in idle states free of active host access. An exemplary memory device includes a memory controller to track a count of idle periods during a specified time window, and to adjust an amount of memory space to be freed by a GC operation in accordance with the count of idle periods. The memory controller can also dynamically reallocate a portion of the memory cells between a single level cell (SLC) cache and a multi-level cell (MLC) storage according to the count of idle periods during the specified time window.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Qing Liang, Deping He, David Aaron Palmer
  • Patent number: 10872018
    Abstract: Systems and methods are provided for preserving data in memory modules of a computer system. An exemplary method can detect that a software preservation process is needed for a computer system, and thereafter performs the software preservation process. The software preservation process can begin by detecting the initiation of a reduced power mode in a computer system. A syncing process of data contents can then be initiated in a processing unit of the computer system. Next, the computer system can automatically save data contents of a memory module. The software preservation process is completed by turning off a power supply unit of the computer system.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: December 22, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventors: Chi-Han Peng, Chun-Ching Yu, Shuen-Hung Wang
  • Patent number: 10866761
    Abstract: An information processing device includes an information processing part performing an information processing with memory information, a first storage device, a storage device connection part connecting with a second storage device, an operation part, and a control part. The control part, in a case where the second storage device is connected to the storage device connection part, stores the memory information stored in the second storage device in the first storage device and removes the memory information from the second storage device, and, in a case where a releasing operation of the connection between the second storage device and the storage device connection part is performed by using the operation part, stores the memory information stored in the first storage device in the second storage device.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: December 15, 2020
    Assignee: KYOCERA Document Solutions Inc.
    Inventor: Yusuke Yoshimoto
  • Patent number: 10867643
    Abstract: A multi-port memory device in communication with a controller includes a memory array for storing data provided by the controller, a first port coupled to the controller via a first controller channel, a second port coupled to the controller via a second controller channel, a processor, and a processor memory local to the processor, wherein the processor memory has stored thereon instructions that, when executed by the processor, cause the processor to: enable data transfer through the first port and/or the second port in response to a first control signal received from the first controller channel and/or a second control signal received from second controller channel, decode at least one of the received first and second control signals to identify a data operation to perform, the identified data operation including a read or write operation from or to the memory array, and execute the identified data operation.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 15, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hingkwan Huen, Changho Choi
  • Patent number: 10866871
    Abstract: Example implementations described herein are directed to a storage descriptor data structure that can represent characteristics of the dataset stored in an underlying volume without requiring the dataset in the volume to be migrated for processing. Such data structures are more compressed than the original data structure and can therefore facilitate storage allocation before the migration is conducted.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: December 15, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Darrell L. Niemann, Bryan Ribaya, Jovi Gacusan