Patents Examined by Jae U Yu
  • Patent number: 10860479
    Abstract: Methods of operating a memory system comprising a plurality of memory devices include loading respective sets of termination information to a subset of memory devices of the plurality of memory devices, and, for each memory device of the subset of memory devices, storing its respective set of termination information to an array of non-volatile memory cells of that memory device. For each memory device of the subset of memory devices, its respective set of termination information comprises address information of the memory system and one or more termination values associated with that address information.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: December 8, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Terry Grunzke
  • Patent number: 10859289
    Abstract: To generate a checkpoint for a virtual machine (VM), first, while the VM is still running, a copy-on-write (COW) disk file is created pointing to a parent disk file that the VM is using. Next, the VM is stopped, the VM's memory is marked COW, the device state of the VM is saved to memory, the VM is switched to use the COW disk file, and the VM begins running again for substantially the remainder of the checkpoint generation. Next, the device state that was stored in memory and the unmodified VM memory pages are saved to a checkpoint file. Also, a copy may be made of the parent disk file for retention as part of the checkpoint, or the original parent disk file may be retained as part of the checkpoint. If a copy of the parent disk file was made, then the COW disk file may be committed to the original parent disk file.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: December 8, 2020
    Assignee: VMware, Inc.
    Inventors: Carl A. Waldspurger, Michael Nelson, Daniel J. Scales, Pratap Subrahmanyam
  • Patent number: 10860494
    Abstract: Embodiments of the present disclosure relate to a method and device for flushing pages from a solid-state storage device. Specifically, the present disclosure discloses a method of flushing pages from a solid-state storage device comprising: determining a first number based on a period length of one flushing cycle and a period length required for building one flushing transaction, the first number indicating a maximum number of flushing transactions that can be built in the flushing cycle; and flushing pages from the solid-state storage device with an upper limit of the first number in the flushing cycle. The present disclosure also discloses a device for flushing pages from a solid-state storage device and a computer program product for implementing steps of a method of flushing pages from a solid-state storage device.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 8, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Liam Li, Xinlei Xu, Jian Gao, Lifeng Yang, Changyu Feng
  • Patent number: 10852989
    Abstract: A method for managing data includes obtaining, by a storage controller, data from a host, applying an erasure coding procedure to the data to obtain a plurality of data chunks and at least one parity chunk, deduplicating the plurality of data chunks to obtain a plurality of deduplicated data chunks, generating storage metadata associated with the plurality of data chunks and the at least one parity chunk, storing, across a plurality of persistent storage devices, the plurality of deduplicated data chunks and the at least one parity chunk, wherein the plurality of persistent storage devices is operatively connected to the storage controller and a second storage controller, storing the storage metadata in the storage controller, and sending a copy of the storage metadata to the second storage controller.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 1, 2020
    Assignee: Dell Products L.P.
    Inventors: Dharmesh M. Patel, Rizwan Ali, Ravikanth Chaganti
  • Patent number: 10852997
    Abstract: An aspect includes determining, in response to an efficiency indicator associated with a destination disk array of a plurality of destination disk arrays, to relocate at least a portion of data currently on a source Logical Unit (LUN) of a source disk array of a plurality of source disk arrays to the destination disk array. The efficiency indicator represents an amount of data on the source LUN that also resides on the destination disk array. The destination disk array supports deduplication. An aspect also includes evaluating multiple destination LUNs of the destination disk array to relocate the data to based on the efficiency indicator and at least one capacity-based factor corresponding to the multiple destination LUNs, selecting one of the multiple destination LUNs to relocate the data based on results of the evaluating, and relocating the data from the source LUN to the selected one of the multiple destination LUNs.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: December 1, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Felix Shvaiger, Arieh Don, Anton Kucherov, Vinay Rao
  • Patent number: 10831670
    Abstract: A method at a computing device for sharing data, the method including defining a dynamically linked data library (DLDL) to include executable code; loading the DLDL from a first process, the loading causing a memory allocation of shared executable code, private data and shared data in a physical memory location; mapping the memory allocation of shared executable code, private data and shared data to a virtual memory location for the first process; loading the DLDL from a second process, the loading causing mapping of the memory allocation of shared executable code and the shared data for the first process to be mapped to a virtual memory location for the second process; and allocating private data in physical memory and mapping to a virtual memory location for the second process.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: November 10, 2020
    Assignee: BlackBerry Limited
    Inventor: Scott Lee Linke
  • Patent number: 10831673
    Abstract: Memory address translation apparatus comprises page table access circuitry to access page table data to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the virtual address space, one or more instances of the translation data; and control circuitry, responsive to an input initial memory address to be translated, to request retrieval of translation data for the input initial memory address from the translation data buffer and, before completion of processing of the request for retrieval from the translation data buffer, to initiate retrieval of translation data for the input initial memory address by the page table access circuitry.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: November 10, 2020
    Assignee: Arm Limited
    Inventors: Andreas Lars Sandberg, Nikos Nikoleris, Prakash S. Ramrakhyani
  • Patent number: 10831660
    Abstract: A processing unit for a multiprocessor data processing system includes a processor core having an upper level cache and a lower level cache coupled to the processor core. The lower level cache includes one or more state machines for handling requests snooped from the system interconnect. The processing unit includes an interrupt unit configured to, based on receipt of an interrupt request while the processor core is in a powered up state, record which of the one or more state machines are active processing a prior snooped request that can invalidate a cache line in the upper level cache and present an interrupt to the processor core based on determining that each state machine that was active processing a prior snooped request that can invalidate a cache line in the upper level cache has completed processing of its respective prior snooped request.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Derek E. Williams, Guy L. Guthrie, Hugh Shen
  • Patent number: 10817433
    Abstract: Systems and methods related to memory paging and memory translation are disclosed. The systems may allow allocation of memory pages with increased diversity in the memory page sizes using page tables dimensioned in a manner that optimizes memory usage by the data structures of the page system.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Altug Koker, Ankur Shah, Murali Ramadoss, Niranjan Cooray
  • Patent number: 10817207
    Abstract: A computer-implemented method for managing a first storage library and a second storage library, according to one embodiment, includes associating a first physical tape and a second physical tape with a logical tape. The associating includes writing a first identifier to an index of the logical tape. The first identifier represents the first physical tape and the first storage library. The associating further includes writing a second identifier to the index of the logical tape. The second identifier represents the second physical tape and the second storage library. The computer-implemented method further includes storing the index of the logical tape in memory, and displaying the logical tape by reading the index from memory as a file system.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: October 27, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hiroshi Itagaki, Tohru Hasegawa, Shinsuke Mitsuma, Tsuyoshi Miyamura, Noriko Yamamoto, Sosuke Matsui
  • Patent number: 10817205
    Abstract: Processing efficiency of a computer using a volume and processing efficiency of another computer using another volume corresponding to the volume can be maintained at high levels. In a computer system, a storage apparatus is able to provide a certain volume to a computer, and another storage apparatus provides data to the computer by causing a virtualization function to point to another volume from the certain volume and copying data from the other volume to the certain volume. An upper limit on the number of pages copiable from the other volume to the certain volume of the storage apparatus is set. A CPU of the other storage apparatus copies data in an amount equal to or smaller than the upper limit from a page among multiple pages of the other volume to a storage region corresponding to a page forming the certain volume of the storage apparatus.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: October 27, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Takaki Nakamura, Hideo Saito, Ken Nomura
  • Patent number: 10809936
    Abstract: A method includes monitoring a given workload running on one or more storage systems to obtain performance data, detecting a given potential performance-impacting event affecting the given workload based at least in part on a given portion of the obtained performance data, and generating a visualization of at least the given portion of the obtained performance data. The method also includes providing the generated visualization as input to a machine learning algorithm, utilizing the machine learning algorithm to classify the given potential performance-impacting event as one of (i) a true positive event affecting performance of the given workload and (ii) a false positive event corresponding to one or more changes in storage resource utilization by the given workload, and modifying provisioning of storage resources of the one or more storage systems responsive to classifying the given potential performance-impacting event as a true positive event affecting performance of the given workload.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: October 20, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Vibhor Kaushik, Zachary W. Arnold
  • Patent number: 10802979
    Abstract: Systems and techniques for dynamic code execution location in heterogeneous memory are described herein. In an system having a first class of memory and second class of memory that are both byte-addressable, an interpreter may be initialized to execute a program from the first class of memory. The initialization may include locating an Interpreter Routine Address Table (IRIT) in the second class of memory and creating counters for routines in the IRIT. A counter for a routine may be modified as it is referenced from the IRIT during execution. The routine may be moved from the first class of memory to the second class of memory in response to the counter passing a threshold. An entry in the IRIT for the routine may be updated with an address in the second class of memory corresponding to the routine.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: October 13, 2020
    Assignee: Intel Corporation
    Inventors: Shu Xu, Tianyou Li, Zidong Jiang, Weiliang Lion Lin, Jinkui Ren, Chaobo Zhu, Xiaokang Qin
  • Patent number: 10795819
    Abstract: Disclosed embodiments relate to a system with configurable cache sub-domains and cross-die memory coherency. In one example, a system includes R racks, each rack housing N nodes, each node incorporating D dies, each die containing C cores and a die shadow tag, each core including P pipelines and a core shadow tag, each pipelines associated with a data cache and data cache tags and being either non-coherent or coherent and one of X coherency domains, wherein each pipeline, when needing to read a cache line, issues a read request to its associated data cache, then, if need be, issues a read request to its associated core-level cache, then, if need be, issues a read request to its associated die-level cache, then, if need be, issues a no-cache remote read request to a target die being mapped to hold the cache line.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Robert Pawlowski, Bharadwaj Krishnamurthy, Vincent Cave, Jason M. Howard, Ankit More, Joshua B. Fryman
  • Patent number: 10795596
    Abstract: A method of performing deduplication by a computing device is provided. The method includes (a) as data is received by the computing device into blocks as part of write requests, creating an entry in a log for each of the blocks, each entry including information about that respective block and a digest computed from that respective block; and (b) after accumulating multiple entries in the log, processing the log for delayed deduplication, the processing including (i) retrieving digests from the log, (ii) performing lookups within a deduplication table of the retrieved digests, and (iii) performing deduplication operations based on the lookups using the information about blocks included within the log. An apparatus, system, and computer program product for performing a similar method are also provided.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 6, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Uri Shabi, Vladimir Shveidel, Ronen Gazit, Alex Soukhman, Maor Rahamim
  • Patent number: 10782883
    Abstract: Disclosed herein are system, method, and computer program product embodiments for the assessing of data reduction potential of a source repository of a source module, by a central module, the generation of data savings potential statistics of the source repository by the central module, and the subsequent generation of visual representation of the statistics, and displaying of the visual representation of data reduction potential information.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: September 22, 2020
    Assignee: SAP SE
    Inventors: Steffen Henning, Mateusz Skrzyniarz
  • Patent number: 10782881
    Abstract: A storage device includes: N (N is an integer of 2 or more) disk devices that records data redundantly, the N disk devices including NAND devices; and processing circuitry that checks a timing of reaching an EOL (End Of Life) for each of the N disk devices; and makes a setting that does not allow to write data into a disk device of the N disk devices for which a predetermined timing before the timing of reaching the EOL has arrived.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: September 22, 2020
    Assignee: BUFFALO INC.
    Inventor: Yasuyuki Yamamoto
  • Patent number: 10776011
    Abstract: A computing system including a memory, a processor and a solid state disk is provided. The memory stores a disk access driver program. The solid state disk includes a storage circuit and a control circuit. The control circuit includes a processing unit, a first access path and a second access path. The processing unit communicates with the processor through the first access path. The processor executes the driver program that enables the processor to process a disk access command for directly accessing the storage circuit of the solid state disk through the second access path.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: September 15, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Cheng-Yu Chen, Chih-Ching Chien, Yen-Chung Chen
  • Patent number: 10776047
    Abstract: Apparatuses and methods related to generating memory characteristic based access commands generating the access commands can include providing a first access command to a memory system of a plurality of memory systems, receiving, at a host coupled to the memory system, data corresponding to characteristics of a memory device of the memory system from a controller of the memory system, where the characteristics are based at least in part on processing of the first access command. Generating access commands can also include generating, at the host, a second access command based on the data and transmitting the second access command to at least the memory system.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 15, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Honglin Sun
  • Patent number: 10776041
    Abstract: A remote agent for providing data protection services to virtual machines includes persistent storage for storing a backup data catalog and a backup manager. The backup manager instantiates a backup agent in a new virtual machine of the virtual machines; obtains a backup data package associated with the new virtual machine using the backup agent, the backup data package specifies assets of the new virtual machine; generates a backup data processing schema for the new virtual machine based on the backup data package; initiates a backup generation for the new virtual machine to store a backup for the new virtual machine in backup storage; processes, using the backup agent, metadata associated with the backup using backup data processing schema to obtain backup data processing schema compliant catalog data; and provides search services for the backup using the backup data processing schema compliant catalog data and the backup data catalog.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: September 15, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Shelesh Chopra, Sunil Yadav, Jayashree B. Radha, Aaditya Rakesh Bansal, Manish Sharma, Sneha Yadav, Amit Jain