Patents Examined by Jae U Yu
  • Patent number: 10671522
    Abstract: A memory controller and a memory system including the same are provided. The memory controller includes a memory storing a flash translation layer (FTL) mapping table, which includes a physical page number (PPN) of a flash memory and a logical page number (LPN) corresponding to the PPN; a central processing unit (CPU) accessing a memory mapped address space to which a logical address corresponding to the LPN is allocated; and an LPN translator receiving the logical address from the CPU, extracting an LPN corresponding to the logical address, reading, from the memory, the FTL mapping table corresponding to the extracted LPN, extracting a PPN corresponding to the extracted LPN, and transmitting the extracted PPN to the CPU.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: June 2, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun Sik Kim
  • Patent number: 10671315
    Abstract: A system, computer program product, and computer-implemented method for selective restore utilizing a blockchain architecture are provided. Embodiments comprise a controller assigned for selectively copying and reconstructing system data stored on a blockchain, the controller comprising at least one memory device with computer-readable program code stored thereon, at least one communication device connected to a network, and at least one processing device. The at least one processing device is configured to execute the computer-readable program code to: establish a connection to a blockchain within a source environment, the blockchain storing system data; selectively clone a section of the blockchain from the source environment; and reconstruct the section of the blockchain in a target environment.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: June 2, 2020
    Assignee: BANK OF AMERICA CORPORATION
    Inventor: Siten Sanghvi
  • Patent number: 10657041
    Abstract: In a data management method for a storage device, the storage device includes a nonvolatile memory device including a plurality of memory blocks. A TRIM-after-COPY command is received from an external host such that a data compaction operation is performed on a first storage region. Valid data stored in the first storage region are internally copied into a second storage region based on the TRIM-after-COPY command. A TRIM operation is performed based on the TRIM-after-COPY command to update a logical-to-physical address mapping table and a valid page bitmap.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Hwan Doh, Joo-Young Hwang
  • Patent number: 10642758
    Abstract: A data storage device includes a memory and a controller coupled to the memory. The controller is configured to receive a compare command from a host, fetch or generate protection information from the host, fetch protection information from the memory, compare the protection information from the host and from the memory, and post a failure notice to the host when the protection information from the host and from the memory do not match. If the protection information from the host and from the memory does match, the controller is further configured to compare data fetched from the host and data fetched from the memory, and post a success notice to the host when both the protection information from the host and the memory match and the data from the host and the memory match.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: May 5, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Shay Benisty
  • Patent number: 10628344
    Abstract: A controlling method, a channel operating circuit and a memory system for executing a plurality of memory dies with single channel are provided. The plurality of memory dies correspond to a plurality of queue sections of a command queue. The controlling method comprises the following steps: A selecting unit selects one of the plurality of queue sections corresponding one of the plurality of memory dies which is riot at a busy state. An executing unit executes a command stored in one of the plurality of queue sections which is selected.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: April 21, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Tzu-Yi Yang, Yi-Chun Liu
  • Patent number: 10621083
    Abstract: A storage system selects from a plurality of physical areas constituting a physical address space as copy source physical areas, one or more non-additionally recordable physical areas each including a fragmented free area, and also selects a recordable physical area as a copy destination physical area. The storage system then writes one or more pieces of live data from the selected one or more copy source physical areas to the free area of the selected copy destination physical area on a per-strip or per-stripe basis, sequentially from the beginning of the free area. If the size of the write target data is such that it is not possible to write the write target data to the free area on a per-strip or per-stripe basis, then the storage system pads the write target data, and writes the padded write target data to the free area on a per-strip or per-stripe basis.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: April 14, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Nakagoe, Akira Yamamoto, Yoshihiro Yoshii
  • Patent number: 10613981
    Abstract: A computational device determines whether one or more tasks are waiting for accessing a cache for more than a predetermined amount of time while least recently used (LRU) based replacement of tracks are being performed for the cache via demotion of tracks from a LRU list of tracks corresponding to the cache. In response to determining that one or more tasks are waiting for accessing the cache for more than the predetermined amount of time, in addition to continuing to demote tracks from the LRU list, a deadlock prevention application demotes tracks from at least one region of a cache directory that identifies all tracks in the cache.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: April 7, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lokesh M. Gupta, Micah Robison, Kyler A. Anderson, Kevin J. Ash, Matthew G. Borlick
  • Patent number: 10606486
    Abstract: In one embodiment, a method includes determining requirements of a storage system by a planning module. The method also includes calculating, by the planning module, an initial configuration for the storage system, the initial configuration specifying a plurality of components that are interoperable to satisfy the requirements of the storage system. In addition, the method includes outputting a purchase file that describes all components that are specified by the initial configuration of the storage system. Moreover, the method includes outputting a configuration file that is interoperable with at least one of the components specified in the purchase file and is configured to automatically initialize the storage system in response to the components of the storage system being installed. In another embodiment, the method includes a management module receiving the configuration file and monitoring performance metrics of a plurality of workloads of the storage system during operation of the storage system.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joshua J. Crawford, Matthew J. Ward, Paul A. Jennas, II, Jason L. Peipelman
  • Patent number: 10606741
    Abstract: A process improves upon the binary buddy allocation approach by salvaging memory units that are typically unused during the binary buddy technique. A free power of 2 size block of memory, retrieved in response to an allocation request, is decomposed by releasing units in power of 2 sizes until the requested size is reached. Released units are made available for subsequent allocation requests. The deallocation of a previously allocated block causes the decomposition of the block into power of 2 size sub-blocks. These sub-blocks may be merged with adjacent free blocks using the binary buddy approach now that units in power of 2 are available. The process keeps free blocks maximally coalesced, so that additional steps of defragmentation or merging are not required. A maximum size value restriction may be attached to some blocks of memory which remains preserved during any of the allocation or deallocation processes.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: March 31, 2020
    Assignee: AIR Technology Holdings Limited
    Inventor: Williams Ludwell Harrison, III
  • Patent number: 10599467
    Abstract: A computing system includes a host and a storage device. The host includes a central processing unit (CPU) and a first volatile memory device. The storage device includes a second volatile memory device and a nonvolatile memory device. The CPU uses the first volatile memory device and the second volatile memory device as a main memory to store temporary data used for operation of the CPU. The CPU determines a swap-out page to be swapped-out of first pages stored in the first volatile memory device, determines a swap-in page to be swapped-in of second pages stored in the second volatile memory device, and exchanges the swapped-out page and the swapped-in page.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Gun Kim, Won-Moon Cheon
  • Patent number: 10599348
    Abstract: A method of processing transactions associated with a command in a storage system is provided. The method includes receiving, at a first authority of the storage system, a command relating to user data. The method includes sending a transaction of the command, from the first authority to a second authority of the storage system, wherein a token accompanies the transaction and writing data in accordance with the transaction as permitted by the token into a partition that is allocated to the second authority in a storage device of the storage system.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 24, 2020
    Assignee: Pure Storage, Inc.
    Inventors: John Hayes, Robert Lee, Igor Ostrovsky, Peter Vajgel
  • Patent number: 10592112
    Abstract: In some examples, a system may include a computing device in communication with at least one storage device. Initially, the computing device may execute a first type of storage software which stores a first volume in a first storage format on the storage device. The computing device may thereafter execute a second type of storage software which configures a second volume in a second storage format on the storage device. Subsequently, the data of the first volume is migrated to the second volume where the data is stored in the second storage format. In some cases, the second storage software may further define a virtual external device on the storage device and define a logical path from the virtual external device to the first volume. The logical path may be used to migrate the data from the first volume to the second volume.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: March 17, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Sakashita, Akira Yamamoto
  • Patent number: 10586592
    Abstract: An example method includes determining a time between writes in place to a particular memory cell, incrementing a disturb count corresponding to a neighboring memory cell by a particular count increment that is based on the time between the writes to the particular memory cell, and determining whether to check a write disturb status of the neighboring memory cell based on the incremented disturb count.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: March 10, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Edward C. McGlaughlin, Samuel E. Bradshaw
  • Patent number: 10585590
    Abstract: According to one embodiment, an electronic device includes a nonvolatile memory that includes blocks and a controller. The controller transmits information to the host. The information indicates a first logical address range corresponding to cold data stored in the nonvolatile memory, and a processing amount for turning a cold block that comprises the cold data into a block to which data is writable. The controller reads the cold data from the nonvolatile memory in accordance with a read command that is received from the host and designates the first logical address range, and transmits the read cold data to the host. The controller writes, to the nonvolatile memory, the cold data that is received with a write command designating the first logical address range from the host.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: March 10, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tetsuya Sunata, Daisuke Iwai, Kenichiro Yoshii
  • Patent number: 10572161
    Abstract: A system is disclosed. The system may include a computer system, which may include a processor that may execute instructions of an application that accesses an object using an object command, and a memory storing the instructions of the application. The computer system may also include a conversion module to convert the object command to a key-value (KV) command. Finally, the system may include a storage device storing data for the object and processing the object using the KV command.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Anand Subramanian, Oscar Prem Pinto
  • Patent number: 10573377
    Abstract: Apparatuses and methods for determining soft data for fractional digit memory cells are provided. One example apparatus can include a controller to determine states of memory cells of a group of memory cells operated as fractional digit memory cells, and determine soft data based, at least partially, on dimensions to which particular memory cells correspond with respect to the group of memory cells, determined states of the memory cells with respect to a state adjacent a state corresponding to a swapping shell, and whether a particular memory cell is a candidate for swapping.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: February 25, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, Patrick R. Khayat, Mustafa N. Kaynak
  • Patent number: 10564867
    Abstract: A peer to peer remote copy operation is performed between a primary storage controller and a secondary storage controller, to establish a peer to peer remote copy relationship between a primary storage volume and a secondary storage volume. Subsequent to indicating completion of the peer to peer remote copy operation to a host, a determination is made as to whether the primary storage volume and the secondary storage volume have identical data, by performing operations of staging data of the primary storage volume from auxiliary storage of the primary storage controller to local storage of the primary storage controller, and transmitting the data of the primary storage volume that is staged, to the secondary storage controller for comparison with data of the secondary storage volume stored in an auxiliary storage of the secondary storage controller.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Brian A. Rinaldi, Micah Robison
  • Patent number: 10558567
    Abstract: A system for optimizing the use of append-only strand data structures is disclosed, with a device driver that transmits strand commands to firmware on a storage device. The storage device firmware executes strand commands natively on the storage device without needing to transmit data over the system bus to copy data to/from a strand saved on the storage device.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: February 11, 2020
    Assignee: Levyx, Inc.
    Inventor: Tony Givargis
  • Patent number: 10554391
    Abstract: Technologies for allocating data storage capacity on a data storage sled include a plurality of data storage devices communicatively coupled to a plurality of network switches through a plurality of physical network connections and a data storage controller connected to the plurality of data storage devices. The data storage controller is to determine a target storage resource allocation to be used by one or more applications to be executed by one or more sleds in a data center, determine data storage capacity available for each of a plurality of different data storage types on the data storage sled, wherein each data storage type is associated with a different level of data redundancy, determine an amount of data storage capacity for each data storage type to be allocated to satisfy the target storage resource allocation, and adjust the amount of data storage capacity allocated to each data storage type.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Steven Miller, Paul Dormitzer
  • Patent number: 10540227
    Abstract: A high performance computing system including processing circuitry and a shared fabric memory is disclosed. The processing circuitry includes processors coupled to local storages. The shared fabric memory includes memory devices and is coupled to the processing circuitry. The shared fabric memory executes a first sweep of a stencil code by sequentially retrieving data stripes. Further, for each retrieved data stripe, a set of values of the retrieved data stripe are updated substantially simultaneously. For each retrieved data stripe, the updated set of values are stored in a free memory gap adjacent to the retrieved data stripe. For each retrieved data stripe, the free memory gap is advanced to an adjacent memory location. A sweep status indicator is incremented from the first sweep to a second sweep.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: January 21, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Charles Johnson, Onkar Patil, Mesut Kuscu, Tuan Tran, Joseph Tucek, Harumi Kuno, Milind Chabbi, William Scherer