Abstract: In 5G, a high degree of automated management and control mechanisms can coordinate various radios in relatively close proximity, via a zone, or in a cluster. Reactive automation coupled with hybrid algorithms utilizing internal radio states and known or expected external events or entities can enable a smart proactive 5G automation. The smart proactive 5G automation can minimize signaling between the radios and provide a hybrid distributed and centralized model utilizing a radio access network intelligent controller to increase spectrum efficiencies. Additionally, the smart proactive 5G automation can provide new service opportunities that can be offered by service providers.
Abstract: An apparatus and method for an asynchronous successive approximation analog-to-digital converter that includes a digital-to-analog converter, a comparator with adjustable integration time electrically coupled to the digital-to-analog converter, and control circuitry electrically coupled to the digital-to-analog converter and the comparator, the control circuitry configured to adjust an integration time of the comparator one or more times during a conversion cycle.
Type:
Grant
Filed:
May 31, 2019
Date of Patent:
June 23, 2020
Assignee:
AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Abstract: A system includes a first device comprising a first clock generating circuit and a transmitter circuit, and a plurality of second devices, each comprising a respective receiver circuit and a respective second clock generating circuit. The first clock generating circuit may be configured to generate a first clock signal, which may provide internal clocking for the first device. The transmitter circuit may be configured to generate a synchronization signal in response to the first clock signal and wirelessly transmit a broadcast signal communicating only the synchronization signal. The respective receiver circuit may be configured to receive the broadcast signal and present a recovered synchronization signal to the respective second clock generating circuit.
Type:
Grant
Filed:
March 25, 2019
Date of Patent:
June 16, 2020
Assignee:
Integrated Device Technology, Inc.
Inventors:
Jagdeep Bal, Elie Ayache, Eduard Van Keulen
Abstract: A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.
Abstract: An amplification subsystem for a communication system includes a downstream amplifier configured to transmit a downstream signal within a first frequency range, an upstream amplifier configured to transmit an upstream signal within a second frequency range, and a bidirectional amplifier configured to selectively transmit a mid-band signal in either of the upstream and downstream direction.
Abstract: Provided are an apparatus and method for a sending end and a receiving end of a wireless communication system, and a soft information estimator. The apparatus for the sending end of the wireless communication system comprises: an interleave division multiple access unit configured to perform interleave processing on information to be sent; and a filter bank multi-carrier unit configured to use a specific sub-carrier chosen in advance to transmit the interleaved information in a parallel manner.
Abstract: Orthogonal differential vector signaling codes are described which support encoded sub-channels allowing transport of distinct but temporally aligned data and clocking signals over the same transport medium. Embodiments providing enhanced LPDDR interfaces are described which are suitable for implementation in both conventional high-speed CMOS and DRAM integrated circuit processes.
Abstract: A symbol mapping device includes a transmission data processing unit receiving two transmission data having the same length, and if the length is a first length, uses the two transmission data as two output data without change, and if the length is less than the first length, adds dummy data to the two transmission data to generate two output data, each data having the first length; a parity addition unit generating two parity-added transmission data based on the two output data, where the two parity-added transmission data each contain parity data added to the transmission data and each have a second length; a shuffle unit extracting two modulation data, being data to be mapped, from the two parity-added transmission data generated by the parity addition unit; and a mapping processing unit mapping the two modulation data to two time slots of constellation points.
Type:
Grant
Filed:
March 22, 2017
Date of Patent:
May 12, 2020
Assignee:
MITSUBISHI ELECTRIC CORPORATION
Inventors:
Keisuke Matsuda, Keisuke Dohi, Tsuyoshi Yoshida
Abstract: In an on-vehicle system, on-vehicle device and gateway are connected via a first network, and the gateway and relay are connected via a second network. The relay performs open-close control of a gate, using a TAS standard of Ethernet TSN. The gateway receives first and second packets including given data, generates a third packet including the first and second packets, and sends the third packets at the transmission timing that is a timing the gate is placed in from closed state to open state to the relay. The relay receives the third packet from the gateway. The relay switches timing to transfer data, for each type of data, and transfer the third packet to the other relay, during a period in which the gate for the type of data is in an open state.
Type:
Grant
Filed:
December 26, 2018
Date of Patent:
May 12, 2020
Assignees:
TOYOTA JIDOSHA KABUSHIKI KAISHA, National University Corporation Nagoya University
Abstract: A multi-level pulse-amplitude modulation receiver system includes an analog equalizer, a digital equalizer, an automatic level tracking engine and an automatic gain controller. The analog equalizer and the automatic gain controller perform signal compensation on a multi-bit quasi-attenuation signal to generate a multi-level compensation signal. The digital equalizer receives the multi-level compensation signal, the positive threshold voltage and the negative threshold voltage, and thereby converts the multi-level compensation signal into a plurality of digital data. The automatic level tracking engine uses the digital data to generate a positive threshold voltage, a negative threshold voltage, at least two positive DC level voltages, and at least two negative DC level voltages, and the positive threshold voltage is an average of the two positive DC level voltages to avoid the nonlinear effect of the analog front end.
Type:
Grant
Filed:
August 22, 2019
Date of Patent:
May 5, 2020
Assignee:
National Chiao Tung University
Inventors:
Wei-Zen Chen, Chia-Tse Hung, Yu-Ping Huang, Yao-Chia Liu
Abstract: To reduce a hardware circuit scale and a memory capacity in a communication system reducing a PAPR. A transmitter includes a transmission processing feedback type FIR filter configured to feed back data outputted from the last stage delay element of a plurality of delay elements included in an FIR filter to the first stage delay element and configured to set an initial value to a delay element in a predetermined position, of the delay elements, and performs transmission processing by using the transmission processing feedback type FIR filter. A receiver includes a reception processing feedback type FIR filter configured similarly to the transmission processing feedback type FIR filter and performs reception processing by using the reception processing feedback type FIR filter.
Abstract: A PAM signaling system utilizes multiple equalizers on each data lane of a serial data bus, each of the equalizers associated with a different signal eye of the serial data bus.
Abstract: The invention provides a communications device which uses a clock circuit for generating a clock signal, the clock circuit comprising a tuneable oscillator. The clock frequency is varied to make sure it remains within a tolerance range, so that the device can continue to receive messages correctly. An error rate of received messages is determined, and in response to the error rate exceeding a threshold, a setting of the resistor arrangement and/or the capacitor arrangement is changed to change the clock signal frequency thereby to lower the error rate.
Abstract: A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.
Abstract: A base station for cancelling a transmitter noise present in a reception band, according to the embodiment of the present invention comprises: a transmitting and receiving unit for transmitting and receiving a signal; an uplink signal detector for detecting a first signal extracted from a reception path of the base station and a second signal extracted by filtering, on the basis of the reception band, a signal transmitted on a transmission path of the base station, and for determining, on the basis of the detection result, whether an uplink signal transmitted from a terminal is included in the first signal; and a processor for determining whether to cancel the transmitter noise depending on whether the uplink signal is included in the first signal.
Abstract: A transmission device includes a first mapper, a second mapper, a converter, a superposer, and a transmitter. The first mapper is configured to map a first bit stream of a first data series to generate a first modulated symbol stream. The second mapper is configured to map a second bit stream of a second data series to generate a second modulated symbol stream. The first modulated symbol stream and the second modulated symbol stream are representable on a complex plane extending in a first direction and a second direction. The converter is configured to convert the second modulated symbol stream in accordance with the first modulated symbol stream only in the first direction on the complex plane. The superposer is configured to superpose the first modulated symbol stream and the second modulated symbol stream converted by the converter, at an amplitude ratio, to generate a multiplexed signal.
Type:
Grant
Filed:
February 8, 2019
Date of Patent:
February 18, 2020
Assignee:
PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Abstract: Methods and apparatuses for transmitting coding indication information and determining a precoding matrix, for use in resolving the problem that the resolution of code words in a codebook generated by using a combination of a beam vector subgroup and column selection cannot be flexibly adjusted.
Type:
Grant
Filed:
July 19, 2016
Date of Patent:
February 18, 2020
Assignee:
China Academy of Telecommunications Technology Beijing
Abstract: Systems and methods are provided for reducing the effects of an impedance mismatch between a communications system and a shared communications medium. A communication system, such as a transceiver within a cable modem, switches between various operating modes including a transmit mode, a receive mode, and a standby mode. The standby mode may be used while the transceiver is in an idle state between modes, such as while changing an amplifier gain states in between transmissions. While transitioning between modes, the impedance presented by the communications system can temporarily fluctuate causing unwanted signal reflections to propagate out of the communications system and on to the shared medium. Circuitry within the communications system, such as transmission circuitry including an adjustable attenuator, may be placed into a hybrid attenuation-isolation mode during the transition causing the magnitude of any unwanted signal reflections to be attenuated and reducing the impact on the shared medium.
Type:
Grant
Filed:
February 22, 2019
Date of Patent:
February 11, 2020
Assignee:
SKYWORKS SOLUTIONS, INC.
Inventors:
Adrian John Bergsma, Peihua Ye, Thomas Obkircher, Peter Harris Robert Popplewell, Gregory Edward Babcock, William J. Domino
Abstract: A radio communication receiver and a method performed by the radio communication receiver for configuring a Notch filter of the radio communication receiver. The method comprises retrieving stored and previously determined filter coefficients from a set of filter coefficients, where the retrieved filter coefficients constitute a fraction of the total number of filter coefficients; and setting the rest of the filter coefficients to one. The method further comprises normalising the retrieved filter coefficients; and transforming the filter coefficients such that the Notch position ends up at the one or more frequencies to be filtered out.
Type:
Grant
Filed:
June 15, 2016
Date of Patent:
January 14, 2020
Assignee:
Telefonaktiebolaget LM Ericsson (publ)
Inventors:
Kazimierz Koziarz, Erik Larsson, Henrik Egnell
Abstract: A receiver performs independent packet detection using synchronization words with orthogonality when multiple signals on which frequency-shift keying is performed coexist. The receiver includes a frequency demodulator generating a quasi-amplitude modulation signal that has a value proportional to frequency shift from the first signal or second signal being received, a sign discriminator discriminating a sign of the generated quasi-amplitude modulation signal, and a multi-binary correlator calculating a first correlation value which is a binary correlation value between the discriminated sign and a first synchronization word and calculating a second correlation value which is a binary correlation value between the discriminated sign and a second synchronization word.
Type:
Grant
Filed:
October 10, 2018
Date of Patent:
December 31, 2019
Assignee:
ABOV Semiconductor co., Ltd.
Inventors:
Sang Young Chu, Ki Tae Moon, Suk Kyun Hong