Abstract: A storage device including repairable volatile memory and a method of operating the same are provided. The storage device includes a non-volatile memory storing user data, a volatile memory buffering the user data and performing a test for detecting a defective cell on a volatile cell array at an idle time of the storage device, and a controller controlling the volatile memory to perform the test at an idle time and storing test information including a test result or a test history in the non-volatile memory.

Abstract: A method for execution by a processing system in dispersed storage and task network (DSTN) that includes a processor, includes: identifying a slice name of a slice in error of a set of slices stored in a set of dispersed storage (DS) units; identifying a number of slice errors of the set of slices; generating a queue entry that includes the slice name of the slice in error, a rebuilding task indicator, an identity of the set of slices, and the number of slice errors; identifying a rebuilding queue based on the number of slice errors, wherein the rebuilding queue is associated with one of: the set of DS units or another set of DS units; and facilitating storing the queue entry in the identified rebuilding queue.

Abstract: A Long-Term Evolution (LTE) E-UTRAN Node B (eNodeB) for use in satellite markets. The LTE eNodeB supports extreme channel latencies without the need for any User Equipment (UE) (e.g., mobile handsets) modifications, independent of the UE release or the technology used by the network operator. The system supports high channel latencies in LTE, though can also be used for other wireless technologies such as GSM, 5G New Radio (NR) or any other technologies with similar procedures to those used in LTE.

Abstract: A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 64800 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).

Abstract: One embodiment of the present disclosure describes a loopback network including a loopback datapath and a plurality of memory devices. The plurality of memory devices may include a first memory device coupled to a first trunk connector of the first loopback datapath via a first branch connector. The plurality of memory devices may also include a second memory device coupled to the first trunk connector of the first loopback datapath via a second branch connector. When data communicated with the first memory device is targeted by loopback parameters, the first memory device may output a first loopback data signal generated based at least in part on the first data to the first loopback datapath, and the second memory device may block output from the second memory device to the first loopback datapath.

Abstract: A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decompression in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decompression engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decompression engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decompression engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.

Abstract: Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise dividing a user data unit into a plurality of data chunks, generating a plurality of error correction code (ECC) codewords and at least one ECC parity block and transmitting the plurality of ECC codewords and the at least one ECC parity block to a plurality of channels of the non-volatile storage device for each of the plurality of ECC codewords and the at least one ECC parity block to be stored in different channels of the plurality of channels.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including physical blocks, and a controller. The controller manages namespaces. The namespaces include at least a first namespace for storing a first type of data, and a second namespace for storing a second type of data having a lower update frequency than the first type of data. The controller allocates a first number of physical blocks as a physical resource for the first namespace, and allocates a second number of physical blocks as a physical resource for the second namespace, based on a request from a host device specifying an amount of physical resources to be secured for each of the namespaces.

Abstract: A method for a dispersed storage network (DSN) begins by determining an I/O (input/output) capacity of a storage level of DSN memory. The method continues by determining a required performance level to meet operational demands of services operating at the storage level. The method continues by setting a storage level throttle rate based on the I/O capacity and the required performance level and determining a remaining I/O performance of the DSN memory to be allocated to a higher storage level.

Abstract: The present invention relates to a memory with error correction function, comprising a data array, an ECC array, a flag bit array, an ECC encoding module, an ECC decoding module, a flag bit generation module and a flag bit detection module; wherein: the flag bit generation module is configured, when data is being written, to generate a flag bit and an encode enable signal, the flag bit being stored in the flag bit array, and the encode enable signal being used to control the operation of the ECC encoding module; the ECC encoding module is configured to encode the data to be written according to the ECC algorithm preset therein so as to generate parity bits; the ECC array is configured to store the generated parity bits; the flag bit detection module is configured, when data is being read, to detect the flag bit and control the operation of the ECC decoding module; and the ECC decoding module is configured to detect and correct erroneous data using the parity bits from the ECC array and the data from the data

Abstract: The present invention relates to a memory with error correction function, comprising a data array, an ECC array, an ECC encoding module, an ECC decoding module, a first data selection module, a second data selection module and a data output module; wherein when data is being written, the first data selection module receives the data to be written, and determines whether to receive the data from the data array in response to a control signal that affects the length of the data; when data is being read, the second data selection module controls the length of the data output from the data output module in response to the control signal that affects the length of the data. The invention further relates to a method of correcting errors in a memory.

Abstract: An inspection method for memory integrity, a non-volatile memory, and an electronic device are provided. The method includes following steps. A threshold voltage of at least one memory cell to-be-inspected in a non-volatile memory is obtained. A data value belonging to the at least one memory cell to-be-inspected is determined by comparing a read voltage and the threshold voltage. When the data value belonging to the at least one memory cell to-be-inspected is determined, a preset voltage is set according to the data value. An offset data value belonging to the at least one memory cell to-be-inspected is obtained by comparing the preset voltage and the threshold voltage of the at least one memory cell to-be-inspected. And, whether the data value and the offset data value belonging to the at least one memory cell to-be-inspected are the same is determined, so as to determine whether an integrity of the memory cell to-be-inspected is defective.

Abstract: A data storage device utilized for storing a plurality of data includes a memory and a controller. The memory includes a plurality of blocks, and each of the blocks includes a plurality of physical pages. The controller is coupled to the memory. When the data storage device is initiated, or when the data size read by a host is greater than a threshold value, the controller inspects the status of the data stored by the physical pages of the memory.

Abstract: In embodiments, an apparatus may comprise random access memory (RAM); an error detecting and/or correcting code (EDCC) encoder to generate and add an error detecting and/or correcting code to a datum being written into the memory for storage; and an EDCC decoder to use the error detecting and/or correcting code added to the datum to correct one or more bits of error in the datum when the datum with the added error detecting and/or correcting code is read back from the RAM. Further, the apparatus may include an error detection and/or correction checker to inject one or more bits of error into the datum when the datum with the added error and/or correcting code is read back from the RAM, and check whether the EDCC decoder is able to correct the one or more bits of error injected into the datum.

Abstract: We disclose a transmitter that uses at least first and second fixed constellations in which the same bit-words are assigned to different respective constellation symbols of different respective transmit energies. The transmitter generates an outgoing data frame by first generating two data frames using the first and second constellations, respectively, and then selecting the one of the two data frames that has the lower overall transmit energy and discarding the other. The first and second constellations are constructed in a manner that enables the transmitter to realize a significant shaping gain. Some embodiments of the transmitter are compatible with the use of forward-error-correction coding and provide a shaping gain for the transmission of both information and parity bits. An example embodiment of the transmitter can advantageously be implemented with relatively low complexity by employing constellation mappers and demappers that operate using relatively small look-up tables.

Abstract: A system and method improve the performance of non-volatile memory storage by offloading parity computations to facilitate high speed data transfers, including direct memory access (DMA) transfers, between a remote host and a non-volatile memory based storage system, such as a flash memory based data storage device (e.g., SSD). In conjunction with writing to non-volatile memory storage, a stripe map is used to target a selected data storage device for parity generation. All data of a stripe is transmitted to the selected data storage device to generate the parity and the generated parity is propagated from the selected data storage device to other data storage devices in the stripe. The data for the stripe may also be propagated from the selected data storage device to the other data storage devices in the stripe.

Abstract: Techniques are described for performing a bit-flipping decoding scheme on a G-LDPC codeword. In an example, a decoding system uses two syndrome tables. The first syndrome table identifies a predefined syndrome for a component codeword that protects a bit of the G-LDPC codeword. This predefined syndrome is identified based on a location of the bit and is used to update a current syndrome of the component codeword. The second syndrome table identifies one or more bit error locations for the component codeword. The bit error locations are identified from the second syndrome table based on the current syndrome of the component codeword, as updated. In an example, the error locations are used to update a reliability of the bit if its location corresponds to one of the error locations. A bit flipping decision is made for the bit based on its reliability.

Abstract: A data encoding method, a data decoding method, and a storage controller are provided. The encoding method includes: obtaining a verification data corresponding to a raw data according to a write command; adding the verification data to the raw data, and obtaining a scrambled data accordingly; and performing an encoding operation on the scrambled data to obtain a codeword data. The decoding method includes: performing a decoding operation on a codeword data to obtain a decoded codeword data, and obtaining a pre-scrambling data accordingly; identifying a verification data and a raw data in the pre-scrambling data; identifying one or more first system data corresponding to the raw data according to a read command; and determining whether the raw data is correct by comparing the one or more first system data and the verification data.

Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.

Abstract: In some embodiments, an integrated circuit may include a memory self-testing circuit and a memory having a plurality of data storage locations, each location having a unique address. The integrated circuit may further include an output including at least one register capable of storing an address of a memory location where an error has been detected during execution of the memory self-testing circuit. Further, the integrated circuit may include an on-chip clock controller (OCC) circuit including a first output to provide a first clock signal and a second output to provide a second clock signal according to a mode of operation. In a scan mode, the OCC circuit may be configured to enable the first clock signal and the second clock signal and to selectively enable the first clock signal and the second clock signal to be mutually exclusive during a scan capture portion of the scan mode.