Abstract: A circuit and methods of operation thereof are provided for robust protection against soft errors. The circuit includes a first set of storage elements coupled to and configured to sample a set of data inputs at a first set of times. The circuit includes a second set of storage elements coupled to and configured to sample the set of data inputs at a second set of times. A first parity generator generates a first parity check for the set of data inputs and a second parity generator generates a second parity check for output of the first set of storage elements. An error correction unit compares the first parity check and the second parity check to detect occurrences of error conditions in the circuit. The error correction unit may control output or operating characteristics of the circuit as a result of error conditions detected.

Abstract: An information processing device according to the present invention includes: a memory; and at least one processor coupled to the memory. The processor performing operations. The operations includes: constructing second data that is acquired, based on first data containing a plurality of observation values in a plurality of times, by stacking the first data with respect to the times, and extracting a constant pattern that is a combination of the observation values having temporal constancy in the first data, based on the second data; generating a difference between the first data and the constant pattern in the time; and extracting a random pattern that is a combination of the observation values without temporal constancy, based on the difference.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may disable ECC functions of the memory devices. When the ECC function is disabled by the host device, the memory device may deactivate various ECC periphery components coupled with an ECC circuit of the memory device to reduce power consumption of the memory device. In some cases, the memory device may disconnect an electrical power supply to the ECC periphery components. In other cases, the memory device may selectively disable the ECC periphery components or block an access command from reaching the ECC periphery components during an access operation. Further, the ECC array may be configured to replace faulty portions of a main array of the memory device when the ECC function is disabled.

Abstract: A method includes receiving a write request to store a data object; identifying object parameters associated with the data object; selecting a memory type based on the identified object parameters; selecting a selected memory based on the memory type; and facilitating storage of the data object in the selected memory, wherein the data object is dispersed error encoded.

Abstract: An output control apparatus that controls opening and closing between an output terminal connected to an external apparatus and a power supply terminal to which power for the external apparatus is supplied is provided. The output control apparatus includes a first switching element and a second switching element that are connected in series between the power supply terminal and the output terminal, a data generation portion that generates output data for turning on and off the first switching element and the second switching element based on a control command received from outside, a first controller that controls drive of the first switching element, and a second controller that controls drive of the second switching element.

Abstract: An encoder apparatus for reliable transfer of a source data block d in a communication system includes an outer transform configured to receive a data container block v and compute an outer transform block u, whereby u=vGout for an outer transform matrix Gout. The encoder apparatus also includes an inner transform configured to receive the outer transform block u and compute a transmitted code block x, whereby x=uGin for an inner transform matrix Gin. The data container block v is obtained from the source data block d and a frozen data block a. The frozen data block a is a predetermined block of symbols. The outer transform matrix Gout and the inner transform matrix form a triangular factorization of a transform matrix G, which optionally is a non-triangular matrix, while the outer transform matrix Gout and the inner transform matrix Gin are strictly upper- and lower-triangular matrices, respectively.

Abstract: Systems, apparatus and methods are provided for providing fast non-volatile storage access with ultra-low latency. A method may comprise dividing a user data unit into a plurality of data chunks, generating a plurality of error correction code (ECC) codewords and at least one ECC parity block and transmitting the plurality of ECC codewords and the at least one ECC parity block to a plurality of channels of the non-volatile storage device for each of the plurality of ECC codewords and the at least one ECC parity block to be stored in different channels of the plurality of channels.

Abstract: The present invention concerns an anti-tearing protection system (1) for a non-volatile memory (3) comprising a first memory block (5) and a second memory block (7), the first and second memory blocks (5, 7) being arranged to store a data set comprising user data and an error detection code obtained based on the user data. The first and second memory blocks (5, 7) can be read in a first read mode for determining logic states of data elements comprised in the data set according to the first read mode. The user data in a respective memory block are considered to be correct according to the first read mode if its error detection code equals a first given value. The first and second memory blocks (5, 7) can further be read in a second read mode for determining the logic states of the data elements comprised in data set according to the second read mode.

Abstract: The voter circuit and method determines a voted output among plural inputs each carrying circular data. To supply the voted output, a statistical average (e.g., mean or median) is computed by grouping the plural inputs into pairs, and for each pair generating a minimum angular difference by selecting the minimum of (a) the absolute difference between the pairs of inputs, and (b) the conjugate of the absolute difference between the pairs of inputs. The voted output is a statistical average generated from the minimum angular difference.

Abstract: Disclosed herein is an apparatus that includes a memory cell array configured to output a read data and a timing signal in response to a read command signal, an input counter configured to update an input count value in response to the timing signal, an output counter configured to update an output count value in response to the read command signal, and a data FIFO circuit having a plurality of data registers, the data FIFO circuit being configured to store the read data into one of the data registers indicated by the input count value and configured to output the read data stored in one of the data registers indicated by the output count value. The output counter is configured to maintain the output count value without updating in response to the read command signal when an active judge signal is in an inactive state.

Abstract: A storage device and a method for operating the storage device are provided. A storage device includes processing circuitry configured to write multi-stream data on a non-volatile memory; generate parity data of the multi-stream data and/or intermediate parity data upon which the parity data is based; store the parity data and/or the intermediate parity data in a first memory; and perform a data swap between the first memory and a second memory, wherein a number of slots of a plurality of slots in the first memory is based on a number of execution units of program buffering of the non-volatile memory.

Abstract: A method and a hardware accelerator device are provided for performing erasure coding on the hardware accelerator device that includes a dedicated buffer memory that is resident on the hardware accelerator device and that is connected to a second device via a bus, the method includes receiving, at the dedicated buffer memory, write data directly from the second device via the bus such that receiving the data at the dedicated buffer memory bypasses a buffer memory connected to a central processing unit (CPU), performing, at the hardware accelerator, an erasure coding operation on the write data received at the dedicated buffer memory to generate parity data based on the received write data, transmitting the parity data directly to a storage device connected to the hardware accelerator device via the bus such that transmitting the parity data bypasses the buffer memory connected to the CPU.

Abstract: The present invention provides a method for accessing a flash memory module, wherein the method comprises: receiving data and a corresponding metadata from a host device; performing a CRC operation upon the data to generate a CRC code; encoding the metadata and the CRC code to generate an adjusted parity code; encoding the data and the adjusted parity code to generate encoded data, wherein the encoded data comprises the data, the adjusted parity code and an error correction code corresponding to the data and the adjusted parity code; and writing the encoded data and the metadata to a page of a block of a flash memory module.

Abstract: A self-test verification device may include one or more first processors, configured to generate an instruction for one or more second processors to perform one or more device self-tests; determine for a received result of the one or more device self-tests, whether the result fulfills a predetermined receive time criterion describing an acceptable time until the result should have been received; determine a difference between the received result and a target result; and if the predefined receive time criterion is fulfilled and if the difference between the received result and the target result is within a predetermined range, generate a signal representing a passed self-test.

Abstract: The present disclosure includes apparatuses and methods for physical page, logical page, and codeword correspondence. A number of methods include error coding a number of logical pages of data as a number of codewords and writing the number of codewords to a number of physical pages of memory. The number of logical pages of data can be different than the number of physical pages of memory.

Abstract: A method for the self-diagnosis of RAM error detection logic of a powertrain controller includes: idling, by a first core, an operation of a second core; testing an error correction code (ECC) module corresponding to a RAM operating by the second core; idling, by the second core, an operation of a core of a plurality of un tested cores; and testing an ECC module corresponding to a RAM operating by the core of the plurality of untested cores.

Abstract: Provided is a rate matching method and device for a Polar code. The method includes: concatenating K information bits and (N?K) frozen bits to generate a bit sequence of N bits, and encoding the bit sequence of N bits by means of a Polar code encoder with a generator matrix of size N×N to generate an initial bit sequence {S0, S1, . . . , SN?1} of bits, where K and N are both positive integers and K is less than or equal to N; dividing a circular buffer into q parts, selecting bits from the initial bit sequence {S0, S1, . . . , SN?1} in a non-repeated manner, and writing the bits into the q parts of the circular buffer according to a predefined rule, where q=1, 2, 3 or 4; and sequentially selecting a bit sequence of a specified length from a predefined starting position in a bit sequence in the circular buffer and taking the bit sequence of the specified length as a bit sequence to be transmitted.

Abstract: Systems, devices, media, and methods are presented for releasing an application feature in incremental stages while monitoring the application for anomalies. The feature includes a package of code and an action setting. The methods in some implementations include identifying active devices on which the application has been installed, monitoring the application according to a set of metrics, activating the feature by changing its action setting for a first segment of the active devices, pausing the feature if an anomaly is detected among the set of metrics, and generating a repair ticket. As long as no anomaly is detected, the activating step proceeds for subsequent segments of the active devices, iteratively, until the release is completed. A feature rank may be used to process and release a plurality of features in order of priority.

Abstract: Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.

Abstract: A memory test method for being implemented by storing corresponding test result data and test parameter data into memory chips when a burn-in test, a high temperature test, a low temperature test, and a normal temperature test are performed on the memory chips. A memory test method for being implemented by storing the corresponding test result data and the test parameter data into the memory chips after the memory chips finish the burn-in test, the high temperature test, the low temperature test, and the normal temperature test. The memory chips can internally store the test result data and the test parameter data after finishing tests through the memory test method of the present disclosure so that relevant personnel can read data to easily trace back test history of the memory chips.