Patents Examined by James C. Kerveros
  • Encoder with mask based galois multipliers
    Patent number: 11012094
    Abstract: A programmable digital data encoder employs error correcting coding that uses Galois field multiplication logic wherein each bit of the product is produced by first applying pre-calculated mask values or mask values calculated via a processor executing code, and then applying an XOR circuit together with the mask bits from the pre-calculated or generated mask. In one example, a set of Galois field multipliers is used wherein each multiplier in the set includes a plurality of 2-bit input AND gate circuits and an m-bit input XOR gate circuit to produce a bit of the product. In one example, there are “m” mask values in a mask table wherein m is the symbol width. A different mask value is applied for each bit of the product. The mask values are each m-bits wide, and are stored, for example, in memory as a small look-up table with m m-bit entries or in m m-bit wide registers.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: May 18, 2021
    Assignee: ATI Technologies ULC
    Inventor: Wing-Chi Chow
  • Systems and methods to wake up memory array
    Patent number: 10998073
    Abstract: Disclosed is an apparatus including a memory device. The memory device includes a memory array, a number of non-volatile memory sections configured to store a copy of operational information for the memory array, and a controller coupled to the number of non-volatile memory sections. The controller can responsive to a first wake-up operation, select a first non-volatile memory section as a starting section to retrieve the copy of operational information. The controller can responsive to a second wake-up operation, select a second non-volatile memory section as the starting section to retrieve the copy of operational information without regard to success of a prior attempt to retrieve the copy of operational information.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: May 4, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Phil Reusswig, Sahil Sharma, Gautam Dusija
  • Built-in self-test (BIST) engine configured to store a per pattern based fail status in a pattern mask register
    Patent number: 10971243
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • Data transmission method, sending device, and receiving device
    Patent number: 10944427
    Abstract: A data transmission method, a sending device, and a receiving device are provided. A sending device obtains information data, encodes the information data by using a quasi-cyclic low-density parity-check (LDPC) code matrix, modulates the encoded data to obtain first data, and sends the first data. A receiving device obtains second data, demodulates the second data to obtain to-be-decoded data, and decodes the to-be-decoded data by using a block matrix in an LDPC code matrix, where the block matrix is a submatrix in the quasi-cyclic LDPC matrix, and in the quasi-cyclic LDPC matrix, a row weight of a row (H?1) is greater than or equal to a row weight of a row H, or a row weight of a row (H?1) is less than or equal to a row weight of a row H. In this way, decoding efficiency can be improved.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: March 9, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Liang Ma, Yuejun Wei
  • Devices and methods for generating a low density parity check code for a incremental redundancy HARQ communication apparatus
    Patent number: 10944425
    Abstract: Devices and methods are disclosed for generating on the basis of a first protograph matrix P1 of size m×n, wherein the first protograph matrix P1 defines a first code H1, a second protograph matrix P2 of size (m+d)×(n+d), wherein the second protograph matrix P2 defines a second code H2. The device comprises a processor configured to: generate an auxiliary protograph matrix P? of size (m+d1)×(n+d1) on the basis of the first protograph matrix P1 using row splitting; generate d2 random integer numbers, wherein d2=d?d1; generate a binary matrix M of size d2×(n?m), wherein rows of the binary matrix M are generated on the basis of the d2 random integer numbers; generate a matrix M? by lifting the binary matrix M; Other operation steps are also included.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: March 9, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Vasily Stanislavovich Usatyuk, Nikita Andreevich Polianskii, Ilya Viktorovich Vorobyev
  • Assigning prioritized rebuild resources optimally
    Patent number: 10942684
    Abstract: An integrity processing unit includes rebuild modules to rebuild one or more encoded data slices in a dispersed storage network (DSN) memory unit. The rebuild modules determine a rebuild rate of the DSN memory unit, and, based on the rebuild rate, a rebuild rate status of the DSN memory unit. When the rebuild rate status is a high rebuild rate status, the rebuild rate to the DSN memory unit is reduced and, when the rebuild rate is not zero, the one or more encoded data slices are rebuilt in the DSN memory unit.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Greg R. Dhuse, Jason K. Resch, Ethan S. Wozniak
  • Data transmission method, data sending device, and data receiving device
    Patent number: 10938514
    Abstract: A data transmission method, a data sending device, and a data receiving device are provided. The method includes: encoding, by a data sending device, information data by using a low-density parity-check (LDPC) code matrix, to obtain a bit sequence, where the bit sequence includes a first bit sequence, and the first bit sequence includes at least one information bit in the bit sequence; interleaving, the first bit sequence to obtain a first interleaved bit sequence; performing, modulation based on the first interleaved bit sequence to obtain a sending signal, and sending the sending signal. The method also includes: demodulating, by a data receiving device, a receiving signal to obtain a soft value sequence; and de-interleaving, the soft value sequence, to obtain a soft value sequence of a first bit sequence. This can improve a capability of an LDPC code resisting burst interference.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: March 2, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiaojian Liu, Yuejun Wei, Xin Zeng
  • Method for accessing code SRAM and electronic device
    Patent number: 10922023
    Abstract: Disclosed is a method for accessing a code Static Random Access Memory (SRAM) and an electronic device. The method is applied to an electronic device including a first controller, a code SRAM and an in circuit emulator (ICE); and the method includes: receiving, by the ICE, a first address at which the first controller accesses the code SRAM; transmitting, by the ICE, a first code to the first controller if the first address is the same as a second address, where the second address is an address corresponding to an abnormal address cell in the code SRAM, and the first code is a correct code of the abnormal address cell; or obtaining, by the ICE, a second code corresponding to the first address from the code SRAM, and transmitting the second code to the first controller, if the first address is different from the second address.
    Type: Grant
    Filed: June 22, 2019
    Date of Patent: February 16, 2021
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Shuang Wu, Dan Liu, Yufeng Liu, Wenhe Jin
  • Apparatus and method for probabilistic error correction of a quantum computing system
    Patent number: 10922166
    Abstract: Apparatus and method including a probabilistic compute element for analyzing measured quantum values and responsively adjusting error correction parameters. For example, one embodiment of an apparatus comprises: a quantum controller to generate physical pulses directed to qubits on a quantum processor in response to operations specified in a quantum runtime; quantum measurement circuitry to measure quantum values associated with the qubits following completion of at least a first cycle of quantum runtime operations; and a probabilistic compute engine to analyze the one or more quantum values using inferencing and to responsively adjust a quantum error correction depth value for minimizing a number of errors to be detected on subsequent cycles of the quantum runtime.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: February 16, 2021
    Assignee: Intel Corporation
    Inventor: Justin Hogaboam
  • System and method for user equipment cooperation
    Patent number: 10924212
    Abstract: An embodiment method includes receiving, by a first user equipment (UE), a message, for a second UE, transmitted over a plurality of resource blocks (RBs) on behalf of a communications controller and determining a plurality of log-likelihood ratios (LLRs) in accordance with the received plurality of RBs. The method also includes transmitting, a subset of the determined LLRs to the second UE.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: February 16, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yu Cao, Amine Maaref, Mohammadhadi Baligh, Jianglei Ma
  • Memory system
    Patent number: 10910066
    Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: February 2, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Tsukasa Tokutomi, Marie Takada
  • Error correction code (ECC) operations in memory
    Patent number: 10901837
    Abstract: The present disclosure includes apparatuses and methods for ECC operation associated with memory. One example apparatus comprises a controller configured to perform an error correction code (ECC) operation on a codeword stored in the memory, wherein the codeword includes a first number of ECC bits and the first number of ECC bits are generated based on an encoding matrix, wherein each row of the encoding matrix has an odd number of bits having a binary value of 1.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Gerard A. Kreifels
  • Method for accessing flash memory module and associated flash memory controller and electronic device
    Patent number: 10884851
    Abstract: The present invention provides a method for accessing a flash memory module, wherein the method comprises: receiving data and a corresponding metadata from a host device; performing a CRC operation upon the data to generate a CRC code; encoding the metadata and the CRC code to generate an adjusted parity code; encoding the data and the adjusted parity code to generate encoded data, wherein the encoded data comprises the data, the adjusted parity code and an error correction code corresponding to the data and the adjusted parity code; and writing the encoded data and the metadata to a page of a block of a flash memory module.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: January 5, 2021
    Assignee: Silicon Motion, Inc.
    Inventor: Tsung-Chieh Yang
  • Performance of a read in a memory system
    Patent number: 10884628
    Abstract: Improving performance of a read in a memory system. Various methods include: reading data from a word line in a memory block, where during the read, associated parameters are generated that include: a value indicative of a throughput time, and a value indicative of a bit error rate (BER); retrieving the value indicative of the throughput time and the value indicative of the BER; and performing a read improvement process if the value indicative of the throughput time is above a threshold value. The method also includes performing the read improvement process by: flagging the memory block if the value indicative of the BER is at or below and expected BER; and performing cleanup operations if the value indicative of the BER is higher than the expected BER.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 5, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Niles Yang, Phil Reusswig, Alexandra Bauche
  • Detecting silent data corruption for mass storage devices
    Patent number: 10877842
    Abstract: One embodiment provides a storage controller. The storage controller includes host data segmentation logic to divide, in response to a write command from a host domain to write a data payload to a storage device, the data payload into a plurality of data segments; cyclic redundancy check (CRC) encode logic to generate a CRC code for each data segment; and CRC reordering encode logic to assign each CRC code to another data segment among the plurality of data segments.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Tung Nguyen, Sri Krishna Karthik Koka
  • Memory system
    Patent number: 10877692
    Abstract: A memory system includes a plurality of first memory chips connected to a first bus, a plurality of second memory chips connected to a second bus, and a controller that is connected to the first and second buses and configured to execute a write operation by performing processes that include selecting one of the plurality of first memory chips based on first information including data reading speed information and/or data writing speed information for the plurality of first memory chips, and selecting one of the plurality of second memory chips based on second information including data reading speed information and/or data writing speed information for the plurality of second memory chips.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: December 29, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Koichi Inoue
  • Error detection using symbol distribution in a system with distribution matching and probabilistic amplitude shaping
    Patent number: 10880037
    Abstract: A signal receiver for interpreting a received signal is provided, the receiver being configured to perform: decoding the received signal so as to form a sequence of symbols hypothesised to represent the content of the received signal; comparing the frequency of occurrence of symbols within the sequence with a predetermined symbol distribution; and if the relative frequency of occurrence of symbols within the sequence of symbols does not match the predetermined distribution, treating the sequence of symbols as being an incorrect representation of the content of the received signal.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: December 29, 2020
    Assignees: Huawei Technologies Duesseldorf GmbH, Technische Universitaet Muenchen
    Inventors: Peihong Yuan, Georg Boecherer, Patrick Schulte, Gerhard Kramer, Ronald Boehnke, Wen Xu
  • Techniques to provide a cyclic redundancy check for low density parity check code codewords
    Patent number: 10855315
    Abstract: Techniques are described for wireless communication. One method includes segmenting a payload into a plurality of code blocks; generating, for each code block, a cyclic redundancy check (CRC); encoding each code block and associated CRC in one or more codewords of a plurality of codewords; and transmitting the codewords. The encoding is based at least in part on a low density parity check code (LDPCC) encoding type. Another method includes receiving a plurality of codewords associated with a payload encoded using a LDPCC encoding type; decoding a set of the codewords associated with the first payload and a CRC; and transmitting one of an acknowledgement (ACK) or a non-acknowledgement (NAK) for the set of the codewords.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: December 1, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jing Sun, Taesang Yoo, Tao Luo
  • Generating and using invertible, shortened Bose-Chaudhuri-Hocquenghem codewords
    Patent number: 10855314
    Abstract: A computer-implemented method for using invertible, shortened codewords is described. The method includes receiving a request to store user data bits in a set of memory devices; expanding the user data bits and an inversion bit to bit locations of a codeword template, wherein the expanding forms expanded inversion and user data bits that collectively include additional bits to represent the user data bits and the inversion bit; generating parity bits for the expanded inversion and user data bits to form a shortened codeword, wherein the shortened codeword comprises the expanded inversion and user data bits, and the parity bits; compressing the shortened codeword to form a compressed shortened codeword; and storing the compressed shortened codeword in the set of memory devices.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: December 1, 2020
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Sivagnanam Parthasarathy
  • Storage device including repairable volatile memory and method of operating the same
    Patent number: 10847244
    Abstract: A storage device including repairable volatile memory and a method of operating the same are provided. The storage device includes a non-volatile memory storing user data, a volatile memory buffering the user data and performing a test for detecting a defective cell on a volatile cell array at an idle time of the storage device, and a controller controlling the volatile memory to perform the test at an idle time and storing test information including a test result or a test history in the non-volatile memory.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: November 24, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-hun Kim, Jun-Ki Sung