Patents Examined by James Cho
  • Patent number: 8362806
    Abstract: Provided is a novel keeper circuit with a pull-up device whose strength changes for different operating supply levels so that the pull-up device is weaker for smaller supply levels and stringer for higher supply levels.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 29, 2013
    Assignee: Intel Corporation
    Inventors: Sapumal B. Wijeratne, Clifford L. Ong, Hans J. Greub, Anandraj Devarajan
  • Patent number: 8138789
    Abstract: Some embodiments provide an IC with configuration context switchers. The IC includes several configurable circuits, each of which configurably performs one of several operations at any given time, based on the configuration data set that it receives at that time. The IC includes several storage circuits for storing several configuration data sets for each of the configurable circuits. The IC also includes a context switching interconnect circuit for switchably connecting the configurable circuit to different sets of storage circuits to receive different sets of configuration data sets. The context switcher includes one or more stages for re-timing the data coming from the configuration storage elements. The stages can include interconnect circuitry or storage circuitry. Some embodiments build one of the stages in the configuration data storage elements. Some embodiments encode the configuration data bits and hence utilize a decoder in the context switcher to decode the encoded configuration data.
    Type: Grant
    Filed: October 4, 2010
    Date of Patent: March 20, 2012
    Assignee: Tabula, Inc.
    Inventors: Trevis Chandler, Joe Entjer, Martin Voogel, Jason Redgrave
  • Patent number: 8111112
    Abstract: A semiconductor device has a first coil structure formed over the substrate. A second coil structure is formed over the substrate adjacent to the first coil structure. A third coil structure is formed over the substrate adjacent to the second coil structure. The first and second coil structures are coupled by mutual inductance, and the second and third coil structures are coupled by mutual inductance. The first, second, and third coil structures each have a height greater than a skin current depth of the coil structure defined as a depth which current reduces to 1/(complex permittivity) of a surface current value. In the case of copper, the coil structures have a height greater than 5 micrometers. The first, second, and third coil structures are arranged in rounded or polygonal pattern horizontally across the substrate with a substantially flat vertical profile.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: February 7, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Kai Liu, Robert Charles Frye
  • Patent number: 8008943
    Abstract: A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: August 30, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae-Sik Yun, Kang-Seol Lee
  • Patent number: 8004212
    Abstract: A VFD drive apparatus in which the filament of a VFD is coupled at a first terminal to an input voltage derived from a voltage source, and at a second terminal to a shunt voltage regulator that establishes a regulated filament current and a regulated cutoff voltage with respect to ground potential. Other electrical loads such as drive circuitry for the anodes and grid of the display are coupled between the second terminal of the filament and ground potential so that at least a portion of the filament current is supplied to such other electrical loads. Power dissipated by the shunt voltage regulator is thereby reduced, and the cost associated with providing additional voltage regulators for the other electrical loads is avoided.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: August 23, 2011
    Assignee: Delphi Technologies, Inc.
    Inventors: Wayne A. Madsen, Andrew R. Betts
  • Patent number: 8004313
    Abstract: Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors. One such buffer may comprise a plurality of pre-drivers wherein each pre-driver of the plurality of pre-drivers is operably coupled to a transistor of a plurality of transistors. The buffer may further comprise one or more clamping devices, wherein at least one transistor of the plurality of transistors has a gate coupled to at least one clamping device of the one or more clamping devices.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: August 23, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Venkatraghavan Bringivijayaraghavan, Jason Brown
  • Patent number: 8004315
    Abstract: The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: August 23, 2011
    Assignee: PDF Solutions, Inc.
    Inventor: Tejas Jhaveri
  • Patent number: 7999490
    Abstract: A light source includes an arc tube having a first electrode and a second electrode that emit light by discharge between the electrodes, and a driving unit that supplies a current between the first electrode and the second electrode and can change at least a waveform of frequency and waveform of the supplied current. The driving unit can perform lighting drive of the arc tube, using a driving waveform formed by combining a first lighting waveform having a maximum current value at a part other than a half-cycle rear end of the waveform and a second lighting waveform having a maximum current value at the half-cycle rear end of the waveform.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: August 16, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Tetsuo Terashima, Kentaro Yamauchi, Takeshi Takezawa, Kazuo Okawa, Keishi Kimura
  • Patent number: 7994825
    Abstract: In an output circuit having a de-emphasis for use in high-speed serial transmission, a circuit for suppressing a fluctuation of a common mode potential which occurs in output amplitude is provided. A positive pole and a negative pole of an output circuit in a serial transmission device for differential transmission having de-emphasis are connected to the respective outputs of a differential circuit that differentially receives outputs of a detector device for a pattern of data to be transmitted, and a detector device for an inverted pattern of the data to be transmitted. When a specific pattern of data to be transmitted and its reverted pattern appear, a current of the output circuit is compensated by the connected differential circuit, thereby enabling a common mode noise to be prevented.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: August 9, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Ushio, Takashi Muto
  • Patent number: 7994822
    Abstract: The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: August 9, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Otsuga, Kenichi Osada, Makoto Saen
  • Patent number: 7990175
    Abstract: An output buffer circuit includes a control unit and an output driver. The control unit generates a control signal in response to a mode signal applied from an internal circuit. The output driver selectively performs a driver operation, a termination operation or an electrostatic discharge (ESD) protection operation in response to the control signal.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: August 2, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kyung-Hoi Koo
  • Patent number: 7986159
    Abstract: With conventional redrivers used for external Serial Advanced Technology Attachment (eSATA), there is no ability to indicated to a host that an external device (like a hard disk drive) is not present. As a result, power is consumed by a host because of nearly continual transmission of communication reset signals. Here, a redriver has been provided that includes a cable disconnect terminal and circuitry within a controller that is able to detect whether an external device is present. This redriver enables a host to be powered down or placed in a low power mode while also enabling the use an eSATA compliant connector.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: July 26, 2011
    Assignee: Texas Instruments Incorporated
    Inventors: Jawaid Ahmad, Matthew D. Rowley
  • Patent number: 7982502
    Abstract: A synchronous circuit design is converted to an asynchronous circuit by converting synchronous circuit logic to an asynchronous circuit logic, and converting one or more asynchronous inputs at a circuit boundary to an asynchronous input to the converted asynchronous circuit logic, such that the converted asynchronous input is operable to generate a token upon observing a change in state on the asynchronous input. One or more asynchronous outputs at a circuit boundary is converted to an asynchronous output from the converted asynchronous circuit logic, such that the converted asynchronous output is operable to output updated data as soon as changed data is received from the converted asynchronous circuit logic in the asynchronous output.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: July 19, 2011
    Assignee: Achronix Semiconductor Corporation
    Inventors: Rajit Manohar, Gael Paul, Marcel Van der Goot, Raymond Nijssen, Christopher LaFrieda, Clinton W. Kelly, Virantha Ekanayake
  • Patent number: 7982504
    Abstract: An interconnection architecture for multilayer circuits includes an array of vias and a CMOS layer configured to selectively access the array of vias according to an address. The interconnection architecture also includes a crossbar stack which includes layers of intersecting wire segments with programmable crosspoint devices interposed between intersecting wire segments. The vias are connected to the wire segments such that each programmable crosspoint device is uniquely addressed and every address within a contiguous address space accesses a programmable crosspoint device.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: July 19, 2011
    Assignee: Hewlett Packard Development Company, L.P.
    Inventor: Warren Robinett
  • Patent number: 7977973
    Abstract: An electronic basic unit for a system on chip comprises a semiconductor substrate and an area on the semiconductor substrate. The area is bounded by a geometric basic shape and the electronic basic unit is formed on the semiconductor substrate and has the form of an integrated circuit. The electronic basic unit further comprises a functional circuit core which determines a function for the electronic basic unit and at least one connecting port at the edges of the geometric basic shape. The at least one connecting port is designed to be coupled to a further connecting port of a further electronic basic unit produced on the semiconductor substrate and being adjacent to the electronic basic unit. The electronic basic unit comprises also a programmable connecting-port controller for controlling data transfers between the electronic basic unit and the further electronic basic unit produced on the semiconductor substrate via the at least one connecting port.
    Type: Grant
    Filed: December 9, 2005
    Date of Patent: July 12, 2011
    Assignee: Infineon Technologies AG
    Inventor: Markus Steiner
  • Patent number: 7977969
    Abstract: A circuit arrangement (10) comprises a circuit terminal (11) for supplying a data signal (DATA) having digital information, a logic circuit (12) that is coupled at an input (22) to the circuit terminal (11) for supplying the digital information, an activation circuit (13), and a voltage regulator (14) that is coupled for activation to an output (18) of the activation circuit (13). The activation circuit (13) comprises an input (16) that is coupled to the circuit terminal (11), a delay element (17) that is coupled to the input (16) of the activation circuit (13), and the output (18), connected to the delay element (17), for emitting an activation signal (SON).
    Type: Grant
    Filed: July 2, 2008
    Date of Patent: July 12, 2011
    Assignee: austriamicrosystms AG
    Inventors: Manfred Lueger, Peter Trattler
  • Patent number: 7969190
    Abstract: A mixed-voltage buffer circuit coupled between a first circuit operative at a first power supply voltage and a second circuit operative at a second power supply voltage. The buffer circuit is connectable to the second power supply voltage and a third power supply voltage and includes an input circuit coupled to the first circuit through a first node and to the second circuit through a second node. The input circuit includes a first part coupled to the first node and an inverter coupled to the second node. The first part provides a signal having a voltage level approximately equal to the third power supply voltage to the inverter in response to a first signal on the first node, and provides a signal having a voltage level approximately equal to the second power supply voltage to the inverter in response to a second signal on the first node.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: June 28, 2011
    Inventors: Che-Hao Chuang, Ming-Dou Ker
  • Patent number: 7969199
    Abstract: The invention provides a reduced complexity layout style based on applying a limited set of changes to an underlying repeated base template. With the templates properly defined in accordance with the characteristic features disclosed, the invention enables efficient implementation of logic circuitry, with a dramatic reduction in the pattern complexity (or number of unique layout patterns at each mask level) for realistically sized designs. This reduction in pattern complexity that the invention provides is particularly important for advanced and emerging semiconductor processes, because it enables effective use of SMO and full-chip mask optimization.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: June 28, 2011
    Assignee: PDF Solutions, Inc.
    Inventor: Tejas Jhaveri
  • Patent number: 7965106
    Abstract: It is an object of the invention to provide a digital circuit which can operate normally regardless of binary potentials of an input signal. A semiconductor device having a correcting unit and a logic unit wherein the correcting unit includes a capacitor, first and second switches, wherein the first electrode of the capacitor is connected to the input terminal and the second electrode of the capacitor is connected to the gate of the transistor in the logic circuit, wherein the first switch controls the connection between a gate and drain of the transistor and the second switch controls the potential to be supplied to the drain of the transistor is provided.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: June 21, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: RE43160
    Abstract: A high-speed differential signaling logic gate includes a 1st input transistor, 2nd input transistor, complimentary transistor, current source, a 1st load, and a 2nd load. The 1st input transistor is operably coupled to receive a 1st input logic signal, which may be one phase of a first differential input signal. The 2nd input transistor is coupled in parallel with the 1st input transistor and is further coupled to receive a 2nd input logic signal, which may be one phase of a 2nd differential input signal. The complimentary transistor is operably coupled to the sources of the 1st and 2nd input transistors and to receive a complimentary input signal, which mimics the other phase of the 1st differential logic signal and the 2nd differential logic signal. The current source sinks a fixed current from the 1st and 2nd input transistors and the complimentary transistor. The 1st load is operably coupled to the drains of the 1st and 2nd input transistors to provide a 1st phase of a differential logic output.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: February 7, 2012
    Assignee: Broadcom Corporation
    Inventor: Tsung-Hsien Lin