Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

Abstract: There is provided a semiconductor device that includes: an output buffer capable of adjusting an impedance based on an impedance adjustment signal, and a through-rate control circuit that adjusts a through rate of the output buffer based on at least the impedance adjustment signal, wherein the through-rate control circuit sets a relatively high through rate when the impedance adjustment signal designates a relatively low impedance, and sets a relatively low through rate when the impedance adjustment signal designates a relatively high impedance.

Abstract: A semiconductor integrated circuit includes: a ladder resistor; a ROM decoder; and a test circuit. The ladder resistor includes a plurality of resistors series-connected to each other and is supplied with a correction voltage at least one of both ends of the series connection and a plurality of connection points in the series connection to generate a plurality of gradation voltages at the plurality of connection points. The ROM decoder selects one of the plurality of gradation voltages generated by the ladder resistor, based on a supplied data signal. The test circuit measures a leakage current in the ROM decoder. The test circuit includes: a plurality of separation units, and a control unit. The plurality of separation units separates the series connection, which is respectively supplied with different power source voltages at both ends, at a certain portion, when the leakage current is measured. The control unit controls separation of the plurality of separation unit corresponding to the data signal.

Abstract: A clockless return to state domino logic gate including a domino circuit and an input circuit. The domino circuit asserts s preset node and an enable node to a first logic state and asserts an output node and a reset node to a second logic state in a preset state, and switches to a latch state when the preset node is pulled to the second state. In the latch state, the domino circuit pulls the output node to the first logic state and pulls the enable node to the second logic state. The domino circuit resets back to the preset state when the first reset node is pulled to the first logic state. The input circuit controls the domino circuit based on collective state of input signals, and is configured to perform a selected logic function using at least one return to state signal without use of a clock signal.

Abstract: An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.

Abstract: A hybrid driving apparatus and a method thereof are provided. The hybrid driving apparatus includes a first driving unit, a second driving unit, and a resistor. The first driving unit has a first output end. The second driving unit has a second output end coupled to a first bonding pad. The resistor is coupled between the first output end and the first bonding pad to serve as a matching impedance. When the driving apparatus operates in a first transmission mode, the first driving unit and the second driving unit jointly drive the first bonding pad. When the driving apparatus operates in a second transmission mode, the first driving unit and the second driving unit drive the first bonding pad and a second bonding pad respectively.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: An output circuit of a semiconductor device includes a signal selector configured to receive first and second input data signals and sequentially outputting the first and second input data signals in response to a phase signal; and an output level controller configured to control a voltage level of an output signal of the signal selector based on the first and second input data signals.

Abstract: A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of transmitting multi-level signals in single-ended and differential modes by current and voltage mode signaling. The signal for transmission can be pre-emphasized for all transmitting modes. The reconfigurable transceiver can dynamically scale bandwidth and power consumption based on performance metrics.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: Disclosed is a logic element (LE) that can provide a number of advantageous features. For example, the LE can be configured to implement register packing and/or a fracturable look up table.

Abstract: A signal transmitting circuit includes a circuit block having a driving circuit and an intra-block transmission line for transmitting a signal from the driving circuit, a circuit block having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between the driving and receiving circuit blocks. The inter-block transmission line is terminated by a resistor having substantially the same impedance as the interblock transmission line. The intra-block transmission lines are provided with a resistance element having a resistance substantially equal to a value derived by subtracting half of an impedance of the inter-block transmission line from an impedance of the intra-block transmission line, to lower signal amplitude and suppress reflections of a signal at branch points along the main interblock transmission line, thereby enabling a high-speed signal transfer.

Abstract: The invention provides a semiconductor device having a current input type pixel in which a signal write speed is increased and an effect of variations between adjacent transistors is reduced. When a set operation is performed (write a signal), a source-drain voltage of one of two transistors connected in series becomes quite low, thus the set operation is performed to the other transistor. In an output operation, the two transistors operate as a multi-gate transistor, therefore, a current value in the output operation can be small. In other words, a current in the set operation can be large. Therefore, an effect of intersection capacitance and wiring resistance which are parasitic on a wiring and the like do not affect much, thereby the set operation can be performed rapidly. As one transistor is used in the set operation and the output operation, an effect of variations between adjacent transistors is lessened.

Abstract: A method for a mix mode driver to accommodate traces of different lengths includes storing in the mix mode driver a set of one or more control signals and coefficient signals for a trace length. The one or more control signals select a number of the stages to generate a variable amplitude data output signal. Each stage is operable to increase or decrease a data signal, and each of the coefficient signals determines the magnitude of increase or decrease of the data input signal by a stage. A method for operating the mix mode driver includes generating the variable amplitude data output signal with one or more of the stages, and providing the variable amplitude data output signal to a trace.

Abstract: Field programmable gate arrays using resistivity-sensitive memories are described, including a programmable cell comprising a configurable logic, a memory connected to the configurable logic to provide functions for the configurable logic, the memory comprises a non-volatile rewriteable memory element including a resistivity-sensitive memory element, an input/output logic connected to the configurable logic and the memory to communicate with other cells. The memory elements may be two-terminal resistivity-sensitive memory elements that store data in the absence of power. The two-terminal memory elements may store data as plurality of conductivity profiles that can be non-destructively read by applying a read voltage across the terminals of the memory element and data can be written to the two-terminal memory elements by applying a write voltage across the terminals.

Abstract: Embodiments generally describe techniques for an integrated circuit having a physical unclonable function (PUF). Example integrated circuits may include an input circuit having an input network, a configurable delay circuit having one or more configurable delay chains, and an output circuit having one or more arbiters, serially coupled together. Each delay chain may include a number of serially coupled configurable switching-delay elements adapted to receive, configurably propagate, and output two delayed signals. Each delay chain may be configured using configuration signals responsively output by the input network in response to challenges provided to the input network. The output circuit may further include an output network to generate combined output signals based on the signals output by the arbiters. Each of the input and/or output networks may comprise combinatorial logic, sequential logic, or another PUF, which may be of the same design. Other embodiments may be disclosed and claimed.

Abstract: An integrated circuit, such as a field programmable gate array or other configurable logic device, has an interconnect circuit selectively configurable to operate in a high-speed mode or in a low-power mode. The interconnect circuit is operable from a higher voltage supply or a lower voltage supply to change operating modes without reconfiguring data paths.

Abstract: A waveguide transition for transitioning from an overmoded waveguide to another waveguide is provided, where one end of the waveguide is configured to connect to a rectangular waveguide and the other end is configured to connect to an elliptical waveguide. The transition has an internal shape having top and bottom walls and two side walls. The top and bottom walls are shaped to join smoothly with waveguides at each end of the transition, while the side walls diminish in height along the length of the transition. The waveguide transition may employ mode filtering to suppress unwanted higher modes. A method of forming waveguide components is also disclosed, involving thixoforming of components in single pieces, the components having internal shapes configured for mold core removal.

Abstract: A device and a method for testing a resistance value of an on-die-termination (ODT) device and a semiconductor device having the same are presented. The device can include a comparator, a storage unit and and an output unit. When in an ODT test operation mode, the comparator compares a reference voltage against an input data input to a pad to determine the resistance value of the ODT device and outputs a determination data on the resistance value of the ODT device corresponding to the determination results. The storage unit stores the output of the comparator in synchronization with a clock signal. When in the ODT test operation mode, the output unit outputs the determination data on the resistance value of the ODT device stored in the storage unit to the pad. Thereby not only is the device configured to determine whether or not a defect of the resistance value of the ODT device exists but the device and the method are able to achieve this task in a substantially shorter testing time period.

Abstract: A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating from an integrated circuit.