Abstract: A verification support system for supporting logic verification of a circuit including a transmitter clock domain and a receiver clock domain, the transmitter clock domain, the system includes a detector for receiving data to be transmitted from the transmitter clock domain, and for detecting a fluctuation of the received data due to any timing fluctuation responsive to the transmitter clock. The system includes an identification unit to identify whether or not any fluctuation of the data determined by the detector is propagated to the output of the combinational logic on the basis of propagation of the received data through at least one of logic gates of the receiver clock domain to combinational logic so as to determine any fluctuation of data that is to be inputted to the combinational logic.

Abstract: A driver circuit and method for generating two complementary output currents from a two-state logic input signal at two outputs for connecting a two-wire conductor provide the following actions: generating from the input signal, an output signal at each output, the amperage of one of the output currents being adjustable by a control signal; analyzing each voltage materializing at the outputs; generating an error signal as a function of the output voltages within each of at least two time slots subsequent to a change in state of the input signal; caching the error signals or signals derived therefrom and adjusting, as a function of cached error signals or of the cached signals as a function thereof, the output current in corresponding time slots subsequent to a resulting change in state of the input signal.

Abstract: A switch controlling circuit, which comprises: a frequency programmable clock signal generator and a plurality of registers. The frequency programmable clock signal generator serves to generate a frequency controllable clock signal. The registers comprises: a first stage register, for receiving an input signal and the frequency controllable clock signal, and for outputting a first output signal, which is utilized to control a first switch device, according to the input signal and the frequency controllable clock signal; and a second stage register, for receiving the first output signal and the frequency controllable clock signal, and for outputting a second output signal, which is utilized to control a second switch device, according to the first output signal and the frequency controllable clock signal.

Abstract: A semiconductor integrated circuit includes logic circuits connected in a plurality of stages, a voltage-level inverting unit that is inserted in a signal transmission path of the logic circuits and inverts a voltage level input to the logic circuits, and an inversion-timing control unit that controls inversion timing for the voltage level inverted by the voltage-level inverting unit.

Abstract: An automatic hold time fixing circuit unit includes a first switch having first and second ends connected to data input and output ports. An input end of a memory element is connected to the second end of the first switch. A second switch includes a first end connected to an output end of the memory element and a second end connected to the data output port. A control circuit includes first and second output terminals and first and second input terminals. The first and second output terminals are connected to control ends of the first and second switches. The first and second input terminals allow input of two clocks to the control circuit for controlling connection or disconnection of the first and second switches. The data stored in the memory element can be utilized to fix a hold time of the data, so that correct data can be obtained at the data output port.

Abstract: In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.

Abstract: In a calibration control circuit, a first clock gate circuit restricts passage of reference update clocks during a calibration period so as to stop a first one of the reference update clocks and supplies the restricted reference update clocks as first update clocks CLK1 to both a hit determination circuit and a second clock gate circuit. The second clock gate circuit 110 passes through the first update clocks CLK1 until reception of a hit signal from the hit determination circuit and delivers second update clocks CLK2 to an up/down counter 106. The up/down counter 106 is operated by the second update clocks CLK2. With this structure, the second update clocks used for adjustment steps can be increased in number during the calibration period.

Abstract: A unit cell for a programmable termination circuit in an integrated circuit and a method for programming such termination circuit are described. In an embodiment, such unit cells may have three n-type and three p-type transistors. A first transistor is coupled to receive a first float control signal. A second transistor is coupled to receive a second float control signal. The third and fourth transistors are coupled to receive a first termination voltage control signal. The fifth and sixth transistors are coupled to receive a second termination voltage control signal. The first float control signal and the second float control signal are a pair of complementary signals.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.

Abstract: A semiconductor device includes a plurality of pads configured to receive a plurality of external signals, an internal circuit configured to perform a predetermined internal operation in response to one of the external signals that is inputted through one of the plurality of pads, and a signal transferring unit configured to receive the external signal, output the external signal to an internal circuit an output signal during a normal mode, and output a fixed signal regardless of changes in the external signal to the internal circuit in a test mode.

Abstract: Various techniques are provided for determining interface characteristics of external devices. In one example, a method of configuring a programmable logic device (PLD) with configuration data stored in one or more external memory devices includes reading by the PLD an interface setup command in a bitstream from an external memory device through a configuration port of the PLD while operating the configuration port in accordance with a first set of interface characteristics. The method also includes adjusting by the PLD the configuration port to operate in accordance with a second set of interface characteristics identified by the interface setup command. The method also includes reading by the PLD configuration data in the bitstream from the external memory device through the configuration port while operating the configuration port in accordance with the second set of interface characteristics. The method also includes programming a configuration memory of the PLD with the configuration data.

Abstract: The invention discloses an active back-end termination circuit, which comprises a first resistor, a first transistor, a second resistor, and a second transistor. The first resistor and the first transistor are connected in series for forming a first impendence unit. A first source of the first transistor is connected to a working voltage with VTT. The second resistor and the second transistor are connected in series for forming a second impendence unit. A second gate and a second drain of the second transistor are connected to the working voltage with VTT. Wherein, the first impendence unit and the second impendence unit are connected in parallel. The first transistor or the second transistor is switched on through a power source, and the first transistor and the second transistor change the impedance actively for matching a load according to the voltage source.

Abstract: Power regulator circuitry for programmable memory elements on programmable logic device integrated circuits is provided. The programmable memory elements may each include a storage element formed from cross-coupled inverters and an address transistor. Address drivers may be used to supply address signals to the address transistors. The power regulator circuitry may include an address power supply circuit that produces a time-varying address power supply voltage to the address drivers and storage element power supply circuits that provide time-varying storage element power supply voltages to the cross-coupled inverters in the storage elements. Unity gain buffers may be used to distribute a reference voltage from a bandgap voltage reference to the power supply circuits. The power supply circuits may use voltage dividers and p-channel metal-oxide-semiconductor control transistors.

Abstract: An input and output circuit apparatus includes a signal generating circuit configured to generate a first signal, an input and output circuit configured to receive the first signal from the signal generating circuit and a second signal to generate an output signal responsive to the first signal and the second signal, an operation test circuit having substantially an identical circuit configuration to the input and output circuit, and configured to receive the first signal from the signal generating circuit and a third signal to generate an output signal responsive to the first signal and the third signal, a check circuit configured to generates a check signal indicative of an operating condition of the operation test circuit in response to the output signal of the operation test circuit, and an adjustment circuit configured to adjust the signal generating circuit in response to the check signal output from the check circuit.

Abstract: Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.

Abstract: A load driving circuit comprising: a bias current circuit configured to generate a bias current having a current value corresponding to a level of a control signal; a control circuit configured to control the level of the control signal so that the bias current is increased and thereafter decreased, when an input signal reaches one logic level; and a driving circuit configured to raise an output voltage for driving a load to a higher logic level in a time corresponding to the current value of the bias current, when the input signal reaches the one logic level, and lower the output voltage to a lower logic level, when the input signal reaches the other logic level.

Abstract: Methods and apparatus are provided for selectively setting a CM voltage for a transceiver, reducing the effect of current mismatch, and generating a voltage step that can be used for receiver detection. A circuit of the invention can include voltage generator circuitry operable to generate a plurality of voltage signals of substantially different voltages. The circuit can also include multiplexer circuitry with voltage inputs coupled to the voltage signals. The multiplexer circuitry can be operable to select a reference signal from among the voltage inputs. In addition, the circuit can include operational amplifier (“op-amp”) circuitry with a first input coupled to the reference signal and a second input coupled to an output signal of the op-amp circuitry.

Abstract: An output buffer provided according to an aspect of the present invention is designed to generate an output signal with a slew rate that is substantially independent of the threshold voltage of transistors contained within. An output buffer provided according to another aspect of the present invention provides output signals with different slew rates depending on the magnitude of the load capacitance at the output node of the output buffer.

Abstract: A semiconductor integrated circuit device comprises a transistor circuit exhibiting inductance at a desired frequency owing to capacitance between electrodes in a MOS transistor, the transistor circuit having an impedance that increases with an increase in frequency; and a first MOS transistor that functions as a source follower having the transistor circuit as a load.

Abstract: A system for signal level shifting in an IC can include a first inverter having a first pull-up device and a pull-down device, wherein the first inverter is operable to receive an input signal having a voltage potential at a logic high that does not disable the first pull-up device. The system can include a second inverter coupled in series to an output of the first inverter, and a control module coupled to the output of the first inverter and an output of the second inverter. Prior to the input signal transitioning to the logic high, the control module is operable to decouple the input signal from the first pull-up device, disable the first pull-up device, and close a feedback loop that latches an output state of the second inverter.