Abstract: The present invention aims at providing a circular waveguide polarizer with high performance and low cost. The circular waveguide polarizer is realized by arranging a plurality of side grooves 12 in a side wall of a circular waveguide 11 along the direction of a pipe axis C1 and by appropriately designing the number, spacing, radial depth, circumferential width, length in the pipe axis direction, and the like. According to this circular waveguide polarizer, disturbance is imparted to a section with a coarse electromagnetic field distribution in a transmission mode to create a phase delay, so that the amount of phase delay does not vary largely with a delicate change in width, depth and length of the side grooves 12. That is, there is little deterioration in characteristics caused by a machining error or the like, and hence it becomes possible to effect mass production and cost reductions.

Abstract: Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a dynamic portion and a static portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock, permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element and, obviating a need for keeper device.

Abstract: A programmable logic integrated circuit device has several features which help it perform according to the PCI Special Interest Group's Peripheral Component Interface (“PCI”) signaling protocol. Some of the registers on the device are closely coupled for data input and output to data signal input/output pins of the device. The clock signal input terminals of at least these registers are also closely coupled to the clock signal input pin of the device. Programmable input delay is provided between the data signal input/output pins and the data input terminals of the above-mentioned registers to help compensate for clock signal skew on the device.

Abstract: A semiconductor integrated circuit technology that does not invite the drop of &agr;-ray resistance of flip-flop circuits even when devices are miniaturized. A data hold circuit according to this semiconductor integrated circuit technology includes at least three flip-flop circuits using the same signal as an input, and a majority logic circuit for outputting a signal in accordance with a logic value of the majority of the output of these flip-flop circuits.

Abstract: Various systems and methods for reducing the power consumption of CSRs (Control and Status Registers) within an integrated circuit (IC) are disclosed. In one embodiment, an IC includes a plurality of CSRs. Each CSR includes one or more flip-flops that are used to store one or more bits of control and/or status information for an associated device on the IC. The IC also includes one or more clock gates. Each clock gate is coupled to provide a gated clock signal to one or more of the flip-flops in a respective one of the CSRs. Each clock gate is configured to output a clock signal as the gated clock signal if a clock enable signal that corresponds to the respective CSR is asserted. The IC also includes one or more clock gating units that are each configured to generate the clock enable signal for a respective one of the CSRs.

Abstract: The present invention provides a semiconductor integrated circuit device and a communication device incorporating same. Two MOS (strong and weak) devices are connected to each control input of a transceiver. Both MOS devices are turned on while the supply voltage is ramping from 0V. The strong device remains on for a period of 10-20 microseconds. The strong MOS device pulls the input to a disabled state against external capacitance which is attempting to pull the input to an enabled state. The weak MOS device remains on while pulling the input to a disabled state. The input is pulled to an enabled state when an external source overcomes the weak MOS device. Once the control input is pulled beyond the input voltage threshold to the enabled state, the weak MOS device will be turned off permanently and the input will revert to a standard CMOS input with infinite input resistance.

Abstract: An integrated circuit is characterized in that circuit parts contained therein are connected to one another via an interface containing at least one scan register chain. The at least one scan register chain is configured such that data can be input into the scan register chain either via the output terminals of one of the circuit parts or via the input and/or output terminals of the integrated circuit. In addition, data can be output from the scan register chain either at the input terminals of one of the circuit parts or at the input and/or output terminals of the integrated circuit.

Abstract: A system for improving the speed of operation of an integrated circuit incorporating long lines includes a first voltage operable to provide power to the circuit. The system also includes a second voltage that is less than the first voltage and a third voltage that is less than the second voltage. The system also includes a node, wherein a first status is indicated when the voltage at the node is the second voltage and a second status is indicated when the voltage at the node is the third voltage. The system also includes an input of a switching element connected to the node wherein the switching element is operable to switch upon the voltage at the node changing between the second voltage and the third voltage.

Abstract: A clocking and synchronization circuitry is disclosed. A plurality of windows is provided to accommodate jitters in a clock with respect to a reference clock. A plurality of delayed state cycles is generated from the clock signal for clocking internal operations within the clocked integrated circuit.

Abstract: A method and apparatus for a multi-level GTL interface signaling buffer utilizing midrail buffer pad clamping are described. The system includes a buffer having a P-kicker pull-up device which pulls up a pad voltage level to an intended overshoot level. A pull-down device pulls down the pad voltage level to a termination voltage level VTT. Consequently, the P-kicker pull-up device and the pull-down device counteract one another to generate a low-voltage midrail overshoot level that is less than or equal to a maximum gate voltage level. The midrail overshoot level that is less than or equal to the maximum gate voltage level in order to prevent gate oxide breakdown to CPU LVGTL input buffer circuits caused by overshoot levels in excess of a maximum gauge voltage level.

Abstract: A hybrid integrated circuit in which the specification can quickly be modified and adjusted without preparing a new mask and without compromising the performance of the hybrid integrated circuit. The hybrid integrated circuit includes a common substrate on which an electrode pattern is formed; a first monolithic semiconductor chip designed as an ASIC; and a second monolithic semiconductor chip designed as an FPGA.

Abstract: A circuit for suppressing false operation of a level shift circuit due to a noise transient, the circuit comprising a first transistor coupled to a voltage source of the level shift circuit and being coupled to pass a current when a noise transient is present on the voltage source an output terminal coupled to the first transistor providing as an injected signal a current proportional to the current in the first transistor to at least one level shift transistor of the level shift circuit to prevent false triggering of the level shift circuit due to the noise transient.

Abstract: A method for compensating a threshold voltage of a neighbor bit, are provided. The method includes the first step of arbitrating the word line voltages applied to bits demanded to be programmed, wherein the the word line voltages are arbitrated according to the threshold voltages of the neighbor bits adjacent to the bits. Next, the bits, to which a same word line voltage should be applied, in the memory cells are distributed to a group of bits with the same word line voltage. Then, the same word line voltage is applied to the bits of the group of bits with the same word line voltage.

Abstract: A technique provides an on-chip voltage to a core portion of an integrated circuit by way of a conversion transistor. The on-chip voltage may be a reduced internal voltage, less than the VCC of the integrated circuit. In an embodiment, the layout (or physical structure) of the conversion transistor is distributed surrounding the core portion. By providing the core with a reduced voltage, the integrated circuit may interface with other integrated circuits compatible with different voltage levels.

Abstract: A circuit selectively adjusts the width of an input pulse. The circuit comprises two stages. The first stage delays a leading edge of the input pulse with respect to a trailing edge of the input pulse in accordance with a first control input. The second stage delays the trailing edge of the input pulse with respect to the leading edge of the input pulse in accordance with a second control input. The input pulse width is adjusted in accordance with a difference between the delay of the leading edge and the delay of the trailing edge.

Abstract: An configurable integrated-circuit device includes a plurality of regions that each contain electronic circuitry. The configurable integrated-circuit device also includes common circuitry adapted to provide at least one signal to at least two regions of the plurality of regions. The common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions.

Abstract: A dynamic logic circuit having reduced sub-threshold leakage current during standby mode comprises a connection to at least one upper power rail, a connection to a lower power rail, a precharge node, and an output node adapted to be charged to the potential of the upper power rail after a precharge signal is received at the precharge node. A latch on the output node is provided to maintain the potential at the output node, along with at least one input node for receiving at least one evaluation signal to maintain the potential at the output node to the voltage of the upper power rail or reduce the potential at the output node to the potential of the lower power rail. A device is coupled to the output node to set the output node to a potential which minimizes the sub-threshold leakage upon receipt of a standby signal to maintain the potential at the output node at the potential of the upper power rail or at the potential of the lower power rail.

Abstract: A circuit that reduces external terminal count of a semiconductor chip, such as a communications chip or other type of chip that requires the generation of configuration codes, by reducing the number of external input terminals required for generating the configuration data. The circuit includes multiplexers, each of which selects output data or configuration data, and includes an output in communication with a respective external output terminal of the chip. A selector is connectable between a selected one of the external output terminals and an external input terminal in communication with a memory to serially input configuration data on that output terminal to the memory to configure the chip. Thus, configuration codes are generated for the chip using a reduced number of external input terminals, thereby reducing the overall external terminal count of the chip. The circuit and chip may be embodied on a network or Ethernet card.

Abstract: A circuit for providing a control signal for a load includes a first switch having a first and a second state, a second switch having a first and a second state coupled to said first switch, a load connected to said first and second switches, protection circuitry for protecting said load from excessive voltage and circuitry for switching said first switch. The circuit is arranged so that when the first switch is in the first state current flows from the load to the first switch and the switching circuitry is arranged to switch the first switch to the second state when the voltage across the load reaches a predetermined value.

Abstract: An automatic driver adjuster and methods using the same are provided that modify off-chip drivers based on load characteristics. The preferred embodiments are preferably automatic and require little or no human intervention. Preferred embodiments of the current invention analyze and determine the impedance of a node and adjust a number of output drivers in response to the impedance of the node, or analyze a resultant waveform of the node, caused by an input waveform, and adjust a number of output drivers in response to the resultant waveform of the node.