Abstract: An integrated circuit apparatus includes a reconfigurable arithmetic operation device and a control device that generates mapping data defining a circuit configuration of the reconfigurable arithmetic operation device whose circuit configuration is changed while a given application is running and another application is newly implemented and run. The control device generates mapping data defining an intermediate configuration to shift from a circuit configuration defined by first mapping data to a configuration defined by final mapping data through the intermediate configuration.

Abstract: Some embodiments of the disclosure include a circuit having differential sides and a capacitive network coupled to differential sides. The circuit further includes a reset network for resetting the first differential side to a first voltage and for resetting the second differential side to a second voltage. Other embodiments are described and claimed.

Abstract: A novel and useful load compensation circuit and associated pre-power amplifier constructed therefrom. The load compensation circuit functions to maintain a nearly constant output impedance of the pre-power amplifier by use of a switch matrix comprising a plurality of transistors. The switch matrix is placed in parallel with the output of the pre-power amplifier (PPA). Transistors are turned on or off within the load compensation switch matrix so as to maintain a nearly constant output impedance of the PPA throughout the entire modulation range. At maximum PPA output power, all transistors in the load compensation switch matrix are turned off thereby minimizing the extra output loading and reducing the overall power output. As output power decreases, additional numbers of transistors in the load compensation switch matrix are turned on so as to maintain a constant output impedance of the PPA.

Abstract: A bipolar pulse generator circuit generates bipolar pulses and provides an impedance transformation. The circuit is amenable for implementation in a variety of configurations depending on the size and pulse width requirements for the design. It also maximizes energy transfer and may be implemented in a straight forward, easy manner. The generator may be implemented with one or two switches in a three, five or more transmission line implementation and may include inductive stub, which is inherent element of transmission line transformers. The generator may also be implemented in a multi-layer folded configuration, with or without the addition of a ground potential conductor. The generator may also be implemented in stacked or/and balanced configurations.

Abstract: In one embodiment, a programmable logic device (PLD) such as a field programmable gate array (FPGA) includes a non-volatile memory adapted to store a first bit, a second bit, and a plurality of configuration data. A plurality of configuration memory cells within the PLD is adapted to receive configuration data transferred from the non-volatile memory. The PLD further includes control logic adapted to determine based on the logic states of the first and second bits stored in the non-volatile memory and prior to any transfer of the configuration data whether to transfer the configuration data from the non-volatile memory to the configuration memory cells.

Abstract: An apparatus for measuring an on-die termination (ODT) resistance includes an ODT controller and a driver. The ODT controller receives a plurality of decoding signals, a first test mode signal, and a second test mode signal to generate a plurality of pull-up signals and a plurality of pull-down signals. The pull-up signals are enabled in response to the decoding signals and the first test mode signal, and the pull-down signals are enabled in response to the decoding signals and the second test mode signal. The driver receives the pull-up signals and the pull-down signals to drive a data terminal. At least one of the decoding signals is enabled by a mode register set (MRS) for setting an ODT mode.

Abstract: An independent control signal is transmitted to each of a driver control unit and an output transistor, so as to prevent the driver control unit and the output transistor from being made to operate at the same time and reduce through-current flows. Since the transistor ratio can be selected easily, the degree of designing flexibility increases and the speed enhancement is achieved.

Abstract: An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.

Abstract: Methods and apparatus for novel routing structures and methods that improve fitting of user-defined functions onto programmable logic devices. In particular, second time fitting is improved. Exemplary structures and methods include allowing product terms to be expanded using inputs from more than one neighboring macrocell by providing multiple expansion and bypassing paths. Also, product term OR shifting prevents macrocell output stages from being buried and made inaccessible, and macrocell outputs are provided on expander word lines, increasing efficiency of those lines, as well as conserving routing resources. Expansion, bypassing, OR shifting, and expander word lines may terminate at logic array block boundaries or may continue beyond these boundaries to other logic array blocks.

Abstract: A superconducting tunable filter is disclosed that has a center frequency and a bandwidth able to be adjusted separately. The superconducting tunable filter includes a superconducting resonator filter pattern formed on a dielectric substrate; a dielectric or magnetic plate above the resonator filter pattern and having a through-hole; a dielectric or magnetic rod inserted in the through-hole; and a position controller which separately controls the position of the dielectric or magnetic plate and the position of the dielectric or magnetic rod relative to the resonator filter pattern.

Abstract: A dielectric substrate includes a filter unit, a non-balance/balance conversion unit, and a connection unit for electrically connecting the filter unit to the non-balance/balance conversion unit which are formed in the dielectric substrate. A first resonator has an electrode formed on the main surface of a fourth dielectric layer and a via hole penetrating through a first to a third dielectric layers and connecting the electrode to a grounding electrode. A second resonator has an electrode formed on the main surface of the fourth dielectric layer and a via hole penetrating through the first to the third dielectric layers and connecting the electrode to the grounding electrode.

Abstract: An antenna is formed integrally into one piece and has a ground plane, a feeding strip and two pairs of radiating patches. The feeding strip is connected integrally to the ground plane. The pairs of the radiating patches are formed symmetrically and integrally on the feeding strip. The antenna formed integrally into one piece simplifies the manufacture of the antenna lowers the manufacturing cost of the antenna.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: There is provided a mobile communication terminal including: a dielectric substrate; a ground surface formed on a first area of the dielectric substrate; a radiation part disposed on a second area where the ground surface is not formed, at a predetermined distance from the dielectric substrate, the radiation part having first and second slots formed thereon; a feeding line formed on the second area of the dielectric substrate and having one end connected to the radiation part; a ground line disposed on the second area of the dielectric substrate at a predetermined distance from the feeding line and having one end connected to the radiation part and another end connected to the ground surface; and a matching ground surface formed on the second area of the dielectric substrate, the matching ground surface disposed in a superimposed relationship with a portion of the radiation part and extending from the ground surface to be capacitively coupled to the radiation part.

Abstract: Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.

Abstract: A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device.

Abstract: An antenna made up of addressable conductive segments, or pixel elements, affixed to the top of each piston in a piston array is presented. The pixel elements can be activated in less than a millisecond to form an antenna array and transmission line pattern using movable pistons and a two-dimensional actuator. Each piston comprises a handle, a bottom conductive segment affixed to the top of the handle, a dielectric segment affixed to the uppermost surface of the bottom conductive segment, and a top conductive segment affixed to the uppermost surface of the dielectric segment. When the piston is not actuated, the top conductive segment forms part of a ground plane. The top conductive segment form part of the transmission line and antenna array patterns, the dielectric segment becomes a dielectric space and the bottom conductive segment forms part of the ground plane when the piston is actuated.

Abstract: A method for configuring a n-way XOR/XNOR circuit comprises providing a plurality of top stacks of PFETs each including at least three PFETs electrically connected between a high logic level and an output logic connection, providing a plurality of bottom stacks of NFETs each including at least three NFETs electrically connected between a low logic level and the output logic connection, connecting a source or a drain of the outermost PFET in each top stack to a source or a drain of a corresponding NFET in each bottom stack to generate inverted logic signals, inputting at least three input logic states to the stacks of PFETs to selectively connect or disconnect the output logic connection to the high logic level, inputting at least three input logic states to the stacks of NFETs to selectively connect or disconnect the output logic connection to the low logic level, and outputting a logic signal from the output logic connection.

Abstract: A method of determining a gain nonlinearity receives a phase difference and generates an output frequency based on the received phase difference. The method reconstructs a waveform by using the output frequency. The method preprocesses the phase difference to generate a comparison waveform. The method compares the reconstructed waveform to the comparison waveform and determines a gain nonlinearity based on the comparison between the reconstructed and comparison waveforms. A modulation system includes a voltage controlled oscillator for receiving an input signal based on a phase difference and generating an output frequency. The system further includes a waveform reconstructor and a comparator. The waveform reconstructor is coupled to the voltage controlled oscillator, and is for reconstructing a waveform based on the output frequency. The comparator is coupled to the waveform reconstructor, and is for comparing the output of the waveform reconstructor with the input signal.

Abstract: A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.